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参数资料
| 型号： | AM29F160DT120EC |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | PROM |
| 英文描述： | Triple 3-Input Positive-AND Gates 14-SOIC -40 to 85 |
| 中文描述： | 1M X 16 FLASH 5V PROM, 120 ns, PDSO48 |
| 封装： | MO-142DD, TSOP-48 |
| 文件页数： | 3/46页 |
| 文件大小： | 914K |
| 代理商： | AM29F160DT120EC |
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Am29F160D
GENERAL DESCRIPTION
The Am29F160D is a 16 Mbit, 5.0 Volt-only Flash
memory device organized as 2,097,152 bytes or
1,048,576 words. Data appears on DQ0-DQ7 or DQ0-
DQ15 depending on the data width selected. The
device is designed to be programmed in-system with
the standard system 5.0 volt V
CC
supply. A 12.0 volt
V
PP
is not required for program or erase operations.
The device can also be programmed in standard
EPROM programmers.
The device offers access times of 70, 90, and 120 ns,
allowing high speed microprocessors to operate
without wait states. The device is offered in a 48-pin
TSOP package. To eliminate bus contention each
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Each device requires only a
single 5.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard
. Com-
mands are written to the command register using stan-
dard microprocessor write timing. Register contents
serve as inputs to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass mode
facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase algorithm
—an internal algorithm that automati-
cally preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6
(toggle)
status bits
. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
VCC detector that automatically inhibits write operations
during power transitions. The
hardware sector protec-
tion
feature disables both program and erase operations
in any combination of sectors of memory. This can be
achieved in-system or via programming equipment.
The
Write Protect (WP#)
feature protects the 16
Kbyte boot sector by asserting a logic low on the WP#
pin, whether or not the sector had been previously pro-
tected.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read boot-up firmware from the Flash memory device.
The device offers a
standby mode
as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
相关PDF资料 |
PDF描述 |
|---|---|
| AM29F160DT120EI | Triple 3-Input Positive-AND Gates 14-SO -40 to 85 |
| AM29F160DT120FC | Triple 3-Input Positive-AND Gates 14-SO -40 to 85 |
| AM29F160DT120FI | Triple 3-Input Positive-AND Gates 14-SO -40 to 85 |
| AM29F160DT75 | Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| AM29F160DT75EC | Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29F160DT-120EI | 制造商:Spansion 功能描述:16M (2MX8/1MX16) 5V, BOOT BLOCK, TOP, TSOP48, IND - Trays |
| AM29F160DT-70EF\\T | 制造商:Spansion 功能描述:FLASH PARALLEL 5V 16MBIT 2MX8/1MX16 70NS 48TSOP - Tape and Reel |
| AM29F160DT-70EF\T | 制造商:Spansion 功能描述:FLASH PARALLEL 5V 16MBIT 2MX8/1MX16 70NS 48TSOP - Tape and Reel |
| AM29F160DT-70EI | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 16Mbit 2M/1M x 8bit/16bit 70ns 48-Pin TSOP |
| AM29F160DT-75EF | 功能描述:闪存 16Mb 75ns 5V Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
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