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| 型号： | AM29F160DT90 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| 中文描述： | 16兆位（2米× 8位/ 1个M x 16位），5.0伏的CMOS只，引导扇区闪存 |
| 文件页数： | 9/46页 |
| 文件大小： | 914K |
| 代理商： | AM29F160DT90 |
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8
Am29F160D
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1.
Am29F160D Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V
IH
), A19:A-1 in byte mode (BYTE# = V
IL
).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
3. The 16 Kbyte boot sector is protected when WP# = V
IL
.
4. In CMOS mode, WP# must be at V
CC
±0.5 V or left floating.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and control-
led by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V
IH
.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
Operation
Read
Write
CE#
L
L
V
CC
±
0.5 V
L
X
OE# WE#
L
H
WP#
X
(Note 3)
RESET#
H
H
V
CC
±
0.5 V
H
L
Addresses
(Note 1)
A
IN
A
IN
DQ0–
DQ7
D
OUT
D
IN
DQ8–DQ15
BYTE#
= V
IH
D
OUT
D
IN
BYTE#
= V
IL
H
L
DQ8–DQ14 = High-Z,
DQ15 = A-1
Standby
X
X
(Note 4)
X
High-Z
High-Z
High-Z
Output Disable
Reset
H
X
H
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Sector Protect
(Note 2)
L
H
L
X
V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Address,
A6 = H, A1 = H,
A0 = L
D
IN
X
X
Sector Unprotect
(Note 2)
L
H
L
X
V
ID
D
IN
X
X
Temporary Sector
Unprotect
X
X
X
(Note 3)
V
ID
A
IN
D
IN
D
IN
High-Z
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PDF描述 |
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