- 您现在的位置：买卖IC网 > PDF目录166214 > AM29F400BB-55EF (SPANSION LLC) Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:55ns; Series:AM29 RoHS Compliant: Yes PDF资料下载
参数资料
| 型号： | AM29F400BB-55EF |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:55ns; Series:AM29 RoHS Compliant: Yes |
| 中文描述： | 256K X 16 FLASH 5V PROM, 55 ns, PDSO48 |
| 封装： | LEAD FREE, MO-142BDD, TSOP-48 |
| 文件页数： | 8/43页 |
| 文件大小： | 856K |
| 代理商： | AM29F400BB-55EF |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页
14
Am29F400B
21505E8 November 11, 2009
D A TA
SH EE T
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “The Erase Resume
mode.” for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
m i ng op erat io n. Th e Byt e Pr ogra m co mm an d
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Note:
See Table 5 for program command sequence.
Figure 2.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
Any comm ands wr it ten to th e chip dur ing th e
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, DQ2, or RY/BY#. See “The
Suspend mode.” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the “Erase/Program Operations” tables in “AC
Characteristics” for parameters, and to Figure 14 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for the sector erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 s begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
相关PDF资料 |
PDF描述 |
|---|---|
| AM29F400BB-55SF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:55ns; Series:AM29 RoHS Compliant: Yes |
| AM29F400BB-70EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| AM29F400BB-90EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| AM29F400BB-90SF | Flash Memory IC; Memory Size:4Mbit; Package/Case:44-SOIC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| AM29F400BT-55EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:55ns; Series:AM29 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29F400BB-55EF\\T | 制造商:Spansion 功能描述:IC 4MEG FLSH X 16 CMOS BOTTOM |
| AM29F400BB-55EF\T | 功能描述:闪存 4M (512KX8/256Kx16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AM29F400BB-55SE\T | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 4Mbit 512K/256K x 8bit/16bit 55ns 44-Pin SO T/R |
| AM29F400BB-55SI | 制造商:Spansion 功能描述: 制造商:Spansion 功能描述:4M 5V BOOT SECTOR |
| AM29F400BB-55SI\\T | 制造商:Spansion 功能描述: |
发布紧急采购，3分钟左右您将得到回复。