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参数资料
| 型号： | AM29LV001BB-90JEB |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | PROM |
| 英文描述： | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 128K X 8 FLASH 3V PROM, 90 ns, PQCC32 |
| 封装： | PLASTIC, LCC-32 |
| 文件页数： | 14/38页 |
| 文件大小： | 221K |
| 代理商： | AM29LV001BB-90JEB |
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Am29LV001B
14
P R E L IM IN A R Y
Characteristics
” for parameters, and to Figure 15 for
timing diagrams.
Note:
See Table 5 for program command sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a
hardware
reset
during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, or DQ2. See “Write Oper-
ation Status” for information on these status bits. When
the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no
longer latched.
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for the sector erase command sequence.
The device does
not
require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 μs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 μs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 μs, the
system need not monitor DQ3.
Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data.
The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a
hardware reset
during the
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
21557C-6
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相关代理商/技术参数 |
参数描述 |
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| AM29LV001BT-55ED | 制造商:Spansion 功能描述:1M (128KX8) 3V, BOOT BLOCK, TOP, TSOP32, COM - Trays |
| AM29LV002BB-90EC | 制造商:Advanced Micro Devices 功能描述: |
| AM29LV002BT-90EF | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 2Mbit 256K x 8bit 90ns 40-Pin TSOP |
| AM29LV002BT-90EI\\T | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 2MBIT 256KX8 90NS 40TSOP - Tape and Reel |
| AM29LV002BT-90EI\T | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 2MBIT 256KX8 90NS 40TSOP - Tape and Reel |
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