- 您现在的位置：买卖IC网 > PDF目录366448 > AM29LV001BT-45RJC (ADVANCED MICRO DEVICES INC) 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory PDF资料下载
参数资料
| 型号： | AM29LV001BT-45RJC |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | PROM |
| 英文描述： | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 128K X 8 FLASH 3V PROM, 45 ns, PQCC32 |
| 封装： | MO-052A, PLASTIC, LCC-32 |
| 文件页数： | 7/38页 |
| 文件大小： | 221K |
| 代理商： | AM29LV001BT-45RJC |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
7
Am29LV001B
P R E L IM IN A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29LV001B Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A16–A0.
2. The in-system method of sector protection/unprotection is available. Sector protection/unprotection can be implemented by
using programming equipment. See the “Sector Protection/Unprotection” section.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command
is necessary in this mode to obtain array data. Stand-
ard microprocessor read cycles that assert valid ad-
dresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I
CC1
in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
The device features an
Unlock Bypass
mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicate the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has de-
tails on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
Operation
CE#
L
L
OE#
L
H
X
H
X
WE#
H
L
X
H
X
RESET#
H
H
V
CC
±
0.3 V
H
L
Addresses (Note 1)
A
IN
A
IN
X
X
X
Sector Address, A6 = L,
A1 = H, A0 = L
Sector Address, A6 = H,
A1 = H, A0 = L
A
IN
DQ0–DQ7
D
OUT
D
IN
High-Z
High-Z
High-Z
Read
Write
Standby
Output Disable
Reset
V
CC
±
0.3 V
L
X
Sector Protect (Note 2)
L
H
L
V
ID
D
IN
, D
OUT
Sector Unprotect (Note 2)
L
H
L
V
ID
D
IN
, D
OUT
Temporary Sector Unprotect
X
X
X
V
ID
D
IN
相关PDF资料 |
PDF描述 |
|---|---|
| AM29LV001BT-45RJCB | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| Am29LV001BT-45RJE | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV001BT-45RJI | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV001BT-55ECB | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV001BT-55EE | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29LV001BT-55ED | 制造商:Spansion 功能描述:1M (128KX8) 3V, BOOT BLOCK, TOP, TSOP32, COM - Trays |
| AM29LV002BB-90EC | 制造商:Advanced Micro Devices 功能描述: |
| AM29LV002BT-90EF | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 2Mbit 256K x 8bit 90ns 40-Pin TSOP |
| AM29LV002BT-90EI\\T | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 2MBIT 256KX8 90NS 40TSOP - Tape and Reel |
| AM29LV002BT-90EI\T | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 2MBIT 256KX8 90NS 40TSOP - Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。