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参数资料
| 型号： | AM29LV200BT-55RFC |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 128K X 16 FLASH 3V PROM, 55 ns, PDSO48 |
| 封装： | REVERSE, MO-142DD, TSOP1-48 |
| 文件页数： | 34/47页 |
| 文件大小： | 1095K |
| 代理商： | AM29LV200BT-55RFC |
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Am29LV200B
September 20, 2005
GENERAL DESCRIPTION
The Am29LV200B is a 2 Mbit, 3.0 volt-only Flash
memory organized as 262,144 bytes or 131,072 words.
The device is offered in 44-pin SO, 48-pin TSOP, and 48-
ball FBGA packages. The word-wide data (x16) appears
on DQ15-DQ0; the byte-wide (x8) data appears on
DQ7-DQ0. This device is designed to be programmed
in-system using only a single 3.0 volt VCC supply. No
VPP is required for write or erase operations. The device
can also be programmed in standard EPRO M
programmers.
This device is manufactured using AMD’s 0.32 m
process technology, and offers all the features and ben-
efits of the Am29LV200, which was manufactured using
0. 5 m pro ces s te chn olo gy. I n ad diti on, the
Am29LV200B features unlock bypass programming
and in-system sector protection/unprotection.
The standard device offers access times of 55, 70, 90
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
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相关代理商/技术参数 |
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| AM29LV256MH120RPGI | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 256MBIT 32MX8/16MX16 120NS 64BGA - Trays |
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| AM29LV320DB120EI | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 120ns 48-Pin TSOP |
| AM29LV320DB120WMI | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 120ns 48-Pin FBGA |
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