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参数资料
| 型号： | AM54BDS128AGT89IT |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封装： | 10 X 10 MM, 0.80 PITCH, FBGA-93 |
| 文件页数： | 1/71页 |
| 文件大小： | 1031K |
| 代理商： | AM54BDS128AGT89IT |
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ADVANCE INFORMATION
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you
evaluate this product. Do not design in this product without contacting the factory. AMD reserves the right to change or discontinue work
on this proposed product without notice.
Publication# 26628
Rev: A Amendment/+1
Issue Date: July 23, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
Am54BDS128AG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Two Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
s Power supply voltage of 1.65 to 1.95 volt
s High performance
— Access time as fast as 70 ns/ 54 Mhz Burst
s Package
— 93-Ball FBGA
s Operating Temperature
— –40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
s Single 1.8 volt read, program and erase (1.65 to 1.95
volt)
s Manufactured on 0.17 m process technology
s Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture: 16Mb/16Mb/16Mb/16Mb
s Programmable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
s Sector Architecture
— Eight 8 Kword sectors and one hundred twenty-six 32
Kword sectors
— Banks A and D each contain four 8 Kword sectors
and thirty-one 32 Kword sectors; Banks B and C
each contain thirty-two 32 Kword sectors
— Eight 8 Kword boot sectors, four at the top of the
address range, and four at the bottom of the address
range
s Minimum 1 million erase cycle guarantee per sector
s 20-year data retention at 125°C
PERFORMANCE CHARCTERISTICS
s Read access times at 54/40 MHz
— Burst access times of 13.5/20 ns @ 30 pF at industrial
temperature range
— Asynchronous random access times of 70 ns (at 30
pF)
— Synchronous latency of 87.5/95 ns
s Power dissipation (typical values, C
L = 30 pF)
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.4 A
Hardware features
s Software command sector locking
s Handshaking: host monitors operations via RDY
output
s Hardware reset input (RESET#)
s WP# input
— Write protect (WP#) function protects sectors 0, 1
(bottom boot) or sectors 132 and 133 (top boot),
regardless of sector protect status
s ACC input: Acceleration function reduces
programming time; all sectors locked when ACC = V
IL
s CMOS compatible inputs, CMOS compatible outputs
s Low V
CC write inhibit
SOFTWARE FEATURES
s Supports Common Flash Memory Interface (CFI)
s Software command set compatible with JEDEC 42.4
standards
s Data# Polling and toggle bits
s Erase Suspend/Resume
— Suspends or resumes an erase operation in one
sector to read data from, or program data to, other
sectors
s Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
SRAM Features
s Power dissipation
— Operating: 3 mA maximum
— Standby: 15 A maximum
s CE1s# and CE2s Chip Select
s Power down features using CE1s# and CE2s
s Data retention supply voltage: 1.0 to 2.2 volt
s Byte data control: LB#s (DQ7–DQ0), UB#s
(DQ15–DQ8)
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