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| 型号： | AM79Q021VC |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 编解码器 |
| 英文描述： | PCM CODEC, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 27/64页 |
| 文件大小： | 911K |
| 代理商： | AM79Q021VC |
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SLAC Products
33
Two-Wire Impedance Matching
Two feedback paths on the QSLAC device synthesize
the two-wire input impedance of the SLIC by providing
a programmable feedback path from VIN to VOUT.
The Analog Impedance Scaling Network (AISN) is a
programmable analog gain of –0.9375 to +0.9375 from
VIN to VOUT . The Z filter is a programmable digital
filter providing an additional path and programming
flexibility over the AISN in modifying the transfer
function from VIN to VOUT. Together, the AISN and the
Z-Filter enable the user to synthesize virtually all
required SLIC input impedances.
Frequency Response Correction and
Equalization
The QSLAC device contains programmable filters in
the receive (R) and transmit (X) directions that may be
programmed for line equalization and to correct any
attenuation distortion caused by the Z filter.
Transhybrid Balancing
The QSLAC device’s programmable B filter is used to
adjust transhybrid balance. The filter has a single pole
IIR section (BIIR) and an eight-tap FIR section (BFIR),
both operating at 16 kHz.
Gain Adjustment
T he Q S LAC de v i c e ’s t r a n sm it path has two
programmable gain blocks. Gain block AX is an analog
gain of 0 dB or 6.02 dB (unity gain or gain of 2.0),
located immediately before the A/D converter. GX is a
digital gain block that is programmable from 0 dB to
+12 dB, with a worst-case step size of 0.1 dB for gain
settings below +10 dB, and a worst-case step size of
0.3 dB for gain settings above +10 dB. The filters
provide a net gain in the range of 0 dB to 18 dB.
T h e Q S LAC d e vice r e cei v e pa t h has t w o
programmable loss blocks. GR is a digital loss block
that is programmable from 0 dB to 12 dB, with a worst-
case step size of 0.1 dB. Loss block AR is an analog
loss of 0 dB or 6.02 dB (unity gain or gain of 0.5),
located immediately after the D/A converter. This
provides a net loss in the range of 0 dB to 18 dB.
An additional 6 dB attenuation is provided as part of
GR, which can be inserted by setting the RG bit of
Command 70/71h. This allows writing of a single bit to
introduce 6 dB of attenuation into the receive path without
having to reprogram GR. This 6 dB loss is implemented
as part of GR and the total receive path attenuation must
remain in the specified 0 to –12 dB range. If the RG bit is
set, the programmed value of GR must not introduce
more than an additional 6 dB attenuation.
Transmit Signal Processing
In the transmit path (A/D), the analog input signal (VIN)
is A/D converted, filtered, companded (for A-law or
-law), and made available to the PCM highway in
A-law, -law, or linear form. If linear form is selected, the
16-bit data will be transmitted in two consecutive time
slots starting at the programmed time slot. The signal
processor contains an ALU, RAM, ROM, and control
logic to implement the filter sections. The B, X, and GX
blocks are user-programmable digital filter sections
with coefficients stored in the coefficient RAM, while
AX is an analog amplifier that can be programmed for
0 dB or 6.02 dB gain. The B, X, and GX filters can also
be o perat ed fr o m a n alte r nat e set of d e fault
coefficients stored in ROM (Commands 24 and 25).
The decimator reduces the high input sampling rate to
16 kHz for input to the B, GX, and X filters. The X filter
is a six-tap FIR section which is part of the frequency
response correction network. The B filter operates on
samples from the receive signal path in order to
provide transhybrid balancing in the loop. The high-
pass filter rejects low frequencies such as 50 Hz or
60 Hz, and may be disabled.
Transmit PCM Interface
The transmit PCM interface transmits a 16-bit linear
code (when programmed) or an 8-bit compressed code
from the digital A-law/-law compressor. Transmit logic
controls the transmission of data onto the PCM
highway through output port selection and time/clock
slot control circuitry. The linear data requires two
consecutive time slots, while a single time slot is
required for A-law/-law data.
In the PCM Signaling state (SMODE = 1), the transmit
time slot following the A-law or
-law data is used for
signaling information. The two time slots form a single
16-bit data block.
The frame sync (FS) pulse identifies time slot 0 of the
transmit frame and all channels (time slots) are
r e f e r enc ed to i t . T he l ogic contains user -
programmable Transmit Time Slot and Transmit Clock
Slot registers.
The Time Slot register is 7 bits wide and allows up to
128 8-bit channels (using a PCLK of 8.192 MHz) in
each frame. This feature allows any clock frequency
between 128 kHz and 8.192 MHz (2 to 128 channels)
in a system. The data is transmitted in bytes, with the
most significant bit first.
The Clock Slot register is 3 bits wide and may be
programmed to offset the time slot assignment by 0 to
7 PCLK periods to eliminate any clock skew in the
system. An exception occurs when division of the
PCLK frequency by 64 kHz produces a nonzero
remainder, R, and when the transmit clock slot is
greater than R. In that case, the R-bit fractional time
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