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参数资料
| 型号： | AM93LC66S |
| 英文描述： | 4096-bits Serial Electrically Erasable PROM |
| 中文描述： | 4096位串行电可擦除可编程ROM |
| 文件页数： | 6/10页 |
| 文件大小： | 188K |
| 代理商： | AM93LC66S |
4096-bits Serial Electrically Erasable PROM
AM93LC66
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
5/10
ATC
Functional Descriptions (Continued)
Write (WRITE)
The WRITE instruction includes 8-bit or 16-bit of
data to be written into the specified register. After
the last data bit has been applied to DI, and before
the next rising edge of SK, CS must be brought
LOW. The falling edge of CS initiates the self-timed
programming cycle.
After a minimum wait of 250ns (5V operation) from
the falling edge of CS (tcs), DO will indicate the
READY/BUSY status of the chip if CS is brought
HIGH. This means that logical "0" implies the
programming is still in progress while logical "1"
indicates the selected register has been written, and
the part is ready for another instruction. (See Figure
6)
Note: The combination of CS HIGH, DI HIGH and
the rising edge of the SK clock, resets the
READY/BUSY flag. Therefore, it is important if you
want to access the READY/BUSY flag, not to reset it
through this combination of control signals.
Before a WRITE instruction can be executed, the
device must be in the WRITE ENABLE (WEN) state.
Write All (WRALL)
The Write All (WRALL) instruction programs all
registers with the data pattern specified in the
instruction. While the WRALL instruction is being
loaded, the address field becomes a sequence of
DON'T-CARE bits. (Shown in Figure 7)
As with the WRITE instruction, if CS is brought
HIGH after a minimum wait of 250ns (tcs), the DO
pin indicates the READY/BUSY status of the chip.
(Shown in Figure 7)
Erase (ERASE)
After the erase instruction is entered, CS must be
brought LOW. The falling edge of CS initiates the
self-timed internal programming cycle. Bringing CS
HIGH after minimum of tcs, will cause DO to indicate
the READ/BUSY status of the chip. To explain this,
a logical "0" indicates the programming is still in
progress while a logical "1" indicates the erase cycle
is complete and the part is ready for another
instruction. (Shown in Figure 8)
Erase All (ERALL)
Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the
entire memory array to a logical "1". (Shown in
Figure 9)
Security Consideration
To protect the entire part against accidental
modification of data, each programming instruction
(WRITE, WRALL, ERASE, and ERALL) must satisfy
two conditions before user initiate self-timed
programming cycle (the falling edge of CS). One is
that the AM93LC66 is at WEN status. The other is
that the VCC value must exceed a lock-out value
which can be adjusted by ANALOG TECHNOLOGY
INC.
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| AM93LC66SA | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66VN | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66VNA | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66VS | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66VSA | 4096-bits Serial Electrically Erasable PROM |
相关代理商/技术参数 |
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| AM93LC66SA | 制造商:ANACHIP 制造商全称:Anachip Corp 功能描述:4096-bits Serial Electrically Erasable PROM |
| AM93LC66VGS | 制造商:ANACHIP 制造商全称:Anachip Corp 功能描述:4096-bits Serial Electrically Erasable PROM |
| AM93LC66VGSA | 制造商:ANACHIP 制造商全称:Anachip Corp 功能描述:4096-bits Serial Electrically Erasable PROM |
| AM93LC66VN | 制造商:ANACHIP 制造商全称:Anachip Corp 功能描述:4096-bits Serial Electrically Erasable PROM |
| AM93LC66VNA | 制造商:ANACHIP 制造商全称:Anachip Corp 功能描述:4096-bits Serial Electrically Erasable PROM |
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