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参数资料
| 型号： | AME9001 |
| 厂商： | AME, Inc. |
| 英文描述： | CCFL BACKLIGHT CONTROLLER |
| 中文描述： | CCFL背光控制器 |
| 文件页数： | 16/27页 |
| 文件大小： | 370K |
| 代理商： | AME9001 |
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AME, Inc.
16
CCFL Backlight Controller
AME9001
level on a cycle by cycle basis. If the OVP pin does not
cross its 250mV threshold once during four successive
clock periods in a row then this fault will be triggered.
This protection is disabled while the SSC ramp is below
3V such as during the initial start up and at the beginning
of every dimming cycle. The 1
st
SSC ramp after power
on reset (or CE enabled) is 150 times slower than sub-
sequent start up ramps. This slow first ramp allows more
time for a cold tube to strike before the chip senses a
fault and shuts down.
In order to enable the first two fault condition checks
then the OVP pin must, indirectly, sense the high volt-
age at the input of the CCFL. The actual CCFL voltage
must be reduced by using either a resistor or capacitor
divider such that in normal operation the voltage at OVP
is higher than 250mV but lower than 3V.
The third fault condition check can be used to monitor
the CCFL current. Specifically, it checks whether the
voltage at the CSDET pin is higher than 250mV. If CSDET
does not cross its 250mV threshold once during 4 suc-
cessive clock cycles then this fault will be triggered. This
protection is disabled while the SSC ramp is below 3V,
such as during the initial start period, and at the begin-
ning of every subsequent dimming cycle. This fault con-
dition is used to check that a reasonable minimum amount
of current is flowing in the tube.
Please note that the application circuit of Figure 2 uses
a resistor divider to drive the OVP pin to a voltage above
250mV but below 3V. That effectively disables the first
two fault condition checks. Some applications may not
require all 3 fault condition checks. The third fault condi-
tion is usually sufficient to detect open circuit faults.
Figure 15 is a simplified schematic of the fault protec-
tion circuitry used in the AME9001. Most of the signals
have been previously defined however some need a little
explanation. The VDDOK signal is a power OK signal
that goes high when the 5V supply (VDD) is valid. The
CHOP signal stops the operation of the switching cir-
cuitry once every dimming cycle for burst mode bright-
ness control. The output signal, FIRST, is high during
the first burst cycle after power is turned on. It causes
the SSC pin to source 150 time less current than on
subsequent dimming cycles. The NORM signal is an
enable signal to the switching circuitry. When it is high
the circuit works normally. When it is low the switching
circuitry stops.
SSC and SSV pins
The SSC pin’s primary role is to define a time period
in which the 2nd and 3rd fault condition (previously de-
scribed) are disabled. This period of time is called the
blanking interval. During the initial start up period after a
power on reset or just after a low to high transition on the
CE pin the SSC pin sources 1uA into an external
capacitor(C3). The voltage on SSC ramps upwards to-
wards VDD. The blanking interval is defined as the time
during which V(SSC) < 3V. Once the voltage at SSC
crosses 3V the blanking interval is finished and all three
fault condition checks are enabled. At the beginning of
the next dimming cycle the SSC pin is pulled to VSS
then allowed to ramp upwards again, however during all
subsequent dimming cycles the SSC pin sources 150uA
instead of 1uA as was the case of the first cycle.
In effect, the two different sourcing currents means that
the first blanking interval is 150 times as long as all sub-
sequent blanking intervals. This allows a cold tube more
time to strike before shutting down due to an undercur-
rent or undervoltage fault. (Please see figure 9 for further
clarification of the blanking function.)
The SSV pin (like the SSC pin) is pulled to ground at
the beginning of every dimming cycle then sources 20uA
into an external capacitor. This creates a 0 to 5 volt
ramp at the SSV pin. This ramp is used to limit the duty
cycle of the PWM gate drive signal available at the OUTA
pin. The SSV pin accomplishes duty cycle limiting by
clamping the COMP voltage to no higher than the SSV
voltage. Because the magnitude of the COMP voltage
is proportional to the duty cycle of the PWM signal at
OUTA the duty cycle starts each dimming cycle at zero
and slowly increases to its steady state value as the
voltage at SSV increases. (Figure 9 shows this opera-
tion.)
This type of duty cycle limiting is commonly called
“soft-start” operation. Soft start operation lessens over-
shoot on start up because the power increases gradually
rather than immediately.
Unlike the SSC pin the current sourced by the SSV
pin remains approximately 20uA during ALL dimming
cycles.
Ringing
Due to the leakage inductances of transformer T1 volt-
ages at the drains of Q3 can potentially ring to values
substantially higher than the ideal value (which is twice
the battery voltage). The application schematic in figure
2 uses a snubbing circuit to limit the extent of the ringing
voltage. Components C9,R8,D2 and D3 make up the
snubbing circuit. The nominal voltage at the common
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相关代理商/技术参数 |
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| AME9001AETH | 制造商:AME 制造商全称:Analog Microelectronics 功能描述:CCFL BACKLIGHT CONTROLLER |
| AME9002 | 制造商:AKM 制造商全称:AKM 功能描述:CCFL Backlight Controller |
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| AME9002AEPH | 制造商:AKM 制造商全称:AKM 功能描述:CCFL Backlight Controller |
| AME9002AETH | 制造商:AKM 制造商全称:AKM 功能描述:CCFL Backlight Controller |
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