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参数资料
| 型号： | AME9001AETH |
| 厂商： | AME, Inc. |
| 英文描述： | CCFL BACKLIGHT CONTROLLER |
| 中文描述： | CCFL背光控制器 |
| 文件页数： | 13/27页 |
| 文件大小： | 370K |
| 代理商： | AME9001AETH |
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AME, Inc.
13
AME9001
CCFL Backlight Controller
Driving the CCFL
Unlike other conventional schemes for driving CCFLs
the secondary winding of the AME9001 method is not
designed to look like a voltage source to the CCFL lamp.
The circuit acts more like a current source (or a power
source). The circuit will increase the duty cycle of Q2
thereby dumping more and more energy across to the
secondary tank circuit until the CCFL tube current
achieves regulation or one of the various fault conditions
is met. There is no special "striking period" as is neces-
sary with some other schemes.
When the circuit starts driving the transformer there is
initially no arc struck in the CCFL. The CCFL load looks
like an open circuit. The voltage across the CCFL will
increase with each successive cycle. Two events may
then happen:
1) The gas inside the CCFL will ionize, the voltage across
the CCFL will drop, the current through the CCFL will
increase, and a stable steady state operating point
will be reached.
OR....
2) One of the three fault conditions will be met shutting
down the circuit:
a) The CCFL tube voltage continues to rise until the
OVP pin is higher than 3.5V at which point the
circuit will shut down.
b) The CCFL voltage fails to rise high enough to keep
the undervoltage portion of the OVP pin from trip-
ping.
c) The CCFL current fails to rise high enough to keep
the undercurrent threshold at the CSDET pin from
tripping.
Note that condition a) can be met at any time while the
AME9001 is enabled. Condition b) and c) can only be
met after the SSC pin has crossed 3V AND four succes-
sive undervoltage events occur in a row. The SSC pin is
pulled to VSS everytime the lamp is turned off, whether
for a dimming cycle, user shutdown or fault occurrence.
It ramps up slowly depending on the size of capacitor C3
connected to the SSC pin. The period of time when the
b) and c) fault checks are disabled is called the "blank-
ing" time. The blanking time occurs from the time SSC
starts to ramp up until it reaches 3V. See Figure 9 for
some idealized waveforms illustrating the behavior just
described.
Control Algorithm
There are 2 major control blocks (loops) within the IC.
The first loop controls the duty cycle of the driving wave-
form. It senses the CCFL current (Figure 1 or 2, resistor
R9 and R10) rectifies it, integrates it against an internal
reference and adjusts the duty cycle to obtain the de-
sired power. This loop uses error amplifier EA1 whose
negative input is pin FB and whose output is COMP. The
positive input of EA1 is connected to a 2.5V reference.
External components, R7 and C8, set the time constant
of the integrator, EA1. In order to slow the response of
the integrator increase the value of the product
(R7 X C8).
The second control block adjusts the brightness by
turning the lamp on and off at varying duty cycles. Each
time the lamp turns on and off is referred to as a “dim-
ming cycle”. At the end of each dimming cycle the SSV
pin is pulled low, this forces COMP low as well due to the
clamping action of Clamp1 shown in Figure 1. At the
beginning of a new dimming cycle COMP tries to increase
quickly but it is clamped to the voltage at the SSV(soft-
start voltage) pin. A capacitor on the SSV pin (C8, Fig-
ure 1), which is discharged at the end of every dimming
cycle, sets the slew rate of the voltage at the SSV pin,
and hence also the maximum positive slew rate of the
COMP pin. [“Dimming cycle” is explained more fully
below]
The BRIGHT and CT2 pins
A user-provided voltage at the BRIGHT pin is compared
with the ramp voltage at the CT1 pin (See Figure 10). As
the voltage at BRIGHT increases the duty cycle of the
dimming cycle (and the brightness of the CCFL) increase.
The frequency of the dimming cycles is set by the value
of the capacitor at pin CT1 (C4 in Figure 1 and 2) and it is
also proportional to the current set by resistor R2. Set-
ting C4 equal to 0.01uF and R2 equal to 47.5k yields a
dimming cycle frequency of approximately 125Hz. The
frequency should vary inversely with the value of C4 ac-
cording to the relation:
Frequency(Hz) = 1/[17 X R2 X C4]
The
brightness may also be controlled by using a vari-
able resistor in place of R10 (See Figure 11). In this
case the BRIGHT pin should be pulled to VDD so that
the CCFL remains on constantly. This method can lead
to flicker at low intensities but it is easy to implement.
Harmonic distortion may also increase since the duty
cycle of the waveform at the gate of Q2 will vary greatly
with brightness. When using burst brightness control
the duty cycle of the driving waveforms should not vary
because the CCFL is running at 100% power or it is turned
off. As long as the battery voltage does not change the
duty cycle of the driving waveform also does not change
greatly. This means that harmonic distortion can be mini-
mized by optimizing the frequency and transformer char-
acteristics for a particular duty cycle rather than a large
range of duty cycle.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AME9002 | 制造商:AKM 制造商全称:AKM 功能描述:CCFL Backlight Controller |
| AME9002AEJH | 制造商:AKM 制造商全称:AKM 功能描述:CCFL Backlight Controller |
| AME9002AEPH | 制造商:AKM 制造商全称:AKM 功能描述:CCFL Backlight Controller |
| AME9002AETH | 制造商:AKM 制造商全称:AKM 功能描述:CCFL Backlight Controller |
| AME9003 | 制造商:AKM 制造商全称:AKM 功能描述:CCFL Backlight Controller |
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