参数资料
型号: AMIS-49250-XTP
厂商: ON Semiconductor
文件页数: 4/22页
文件大小: 0K
描述: IC TXRX FIELDBUS MAU 44NQFP
标准包装: 2,500
类型: 收发器
驱动器/接收器数: 1/1
规程: MDS-MAU
电源电压: 4.75 V ~ 6.2 V
安装类型: 表面贴装
封装/外壳: 44-VFQFN 裸露焊盘
供应商设备封装: 44-NQFP(7x7)
包装: 带卷 (TR)
AMIS-492x0
The SHUNT pin is normally connected to VCC. It is possible to insert a resister between VCC and SHUNT to measure the shunt current.
Its value should be small enough to keep VDS (voltage between SHUNT pin and SGND pin) larger than 2.5V (i.e., resistor must be less
than 100
Ω.).
Since the internal transistor can sink as much as 25mA, no additional circuit is necessary in most cases. Note that the drain current
must not exceed 25mA because no protection is implemented for the internal transistor. If you do not need the shunt regulator, you
should connect SHUNT and SHSETIN pins to GND and open SHSET pin. Then VCC must be supplied from another source.
4.2.2. Series Regulator
The series regulator produces a regulated voltage at the VO pin from VCC. If you connect SRAO and SRTR pins together, the internal
amplifier will regulate the input voltage at SRSETIN pin to equal VREF. An internal feedback signal is generated to produce a voltage
equal to VREF at pin SRSET. If you connect SRSET and SRSETIN pins, the series regulator supplies 3V at pin VO. A capacitor (CD in
μF or larger capacity is necessary to stabilize this regulator. The capacitor is expected to have an ESR resistor for the
circuit to be stable. If the capacitor is low, a series resistor with the cap load will help stabilize the circuit).
SRSET
SRTR
SRAO
SRSETIN
VO
May
Supply
VDD
Series Regulator
(External Configuration)
13
16
12
14
15
R4
R5
N/C
Rsr
1.54Rsr
20mA (Max)
A7
Cfb1
40pF
VREF
Cc2
20pF
VCC
CD
SRSET
SRTR
SRAO
SRSETIN
VO
May
Supply
VDD
13
16
12
14
15
Rsr
1.54Rsr
20mA (Max)
A7
Cfb1
40pF
VREF
Cc2
20pF
VCC
CD
Series Regulator
(Internal Configuration)
Figure 5: Series Regulator
The supply current must not exceed 20mA because no current limiting is applied to the internal transistor. You can increase VO voltage
up to 3.5V by dividing VO with an external network to supply the appropriate voltage to pin SRSETIN. In this case, pin SRSET must be
kept open. The drain-source voltage of the internal transistor must be larger or equal to 2V. If this condition is not satisfied, you may
need an external P-channel JFET to create the desired low voltage-drop regulator. The output voltage is determined by the following
equation.
VO = VREF
× (1 + R4/R5)
4.2.3. Low Voltage Detectors
Low voltage detectors are included to monitor supply voltages and generate “power fail” signals. The low voltage alarms are detected
by sensing the voltage on pins SHSETIN and SRSETIN. These pins also provide feedback for the shunt and series regulators. If the
voltage on the SHSETIN pin is lower than the threshold, VTH9 (90 percent VREF), N_PFAIL1 goes low. Typically SHSETIN monitors
the analog rail voltage VCC. If the voltage on the SRSETIN pin is lower than the threshold, VTH9, N_PFAIL2 goes low. Typically
SRSETIN monitors the digital rail voltage VDD.
Both outputs are open drain, so a resistor will be required. If you do not use one of these pins, it should be connected to GND. You
can also add capacitors to delay these signals. In this case, sink current must not exceed the maximum value.
If you do not wish to use one of the low voltage detectors its corresponding output pin should be connected to GND.
Rev. 6 | Page 12 of 22 | www.onsemi.com
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