参数资料
型号: AMIS30622C6227RG
厂商: ON Semiconductor
文件页数: 8/50页
文件大小: 0K
描述: IC MOTOR DVR MICROSTP I2C 20SOIC
标准包装: 1,500
应用: 步进电机驱动器
评估套件: 可供
输出数: 1
电流 - 输出: 800mA
电源电压: 6.5 V ~ 29 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC
包装: 带卷 (TR)
AMIS ? 30622
AC PARAMETERS
The AC parameters are guaranteed for temperature and V BB in the operating range unless otherwise specified.
Table 6. AC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
POWERUP
T pu
Power ? up time
Guaranteed by design
10
ms
INTERNAL OSCILLATOR
f osc
Frequency of internal oscillator
V BB = 14 V
3.6
4.0
4.4
MHz
I 2 C TRANSCEIVER (STANDARD MODE)
f SCL
t HD,START
t LOW
t HIGH
t SU,START
SCL clock frequency
Hold time (repeated) START condition. After
this period the first clock pulse is generated.
LOW period of the SCK clock
HIGH period of the SCK clock
Set ? up time for a repeated START condition
4.0
4.7
4.0
4.7
100
kHz
m s
m s
m s
m s
t HD,DATA
SDA
SCK
Data hold time for I 2 C bus devices
0
(Note 16)
3.45
(Note 17)
m s
t SU,DATA
t R
t F
t SU,STOP
t BUF
Data set ? up time
Rise time of SDA and SCK signals
Fall time of SDA and SCK signals
Set ? up time for STOP condition
Bus free time between STOP and START
condition
250
4.0
4.7
1.0
0.3
ns
m s
m s
m s
m s
I 2 C TRANSCEIVER (FAST MODE)
f SCL
t HD,START
t LOW
t HIGH
t SU,START
SCL clock frequency
Hold time (repeated) START condition. After
this period the first clock pulse is generated.
LOW period of the SCK clock
HIGH period of the SCK clock
Set ? up time for a repeated START condition
0.6
1.3
0.6
0.6
360
kHz
m s
m s
m s
m s
t HD,DATA
t SU,DATA
SDA
SCK
Data hold time for
Data set ? up time
I 2 C
bus devices
0
(Note 16)
100
(Note 18)
0.9
(Note 17)
m s
ns
t R
t F
t SU,STOP
t BUF
Rise time of SDA and SCK signals
Fall time of SDA and SCK signals
Set ? up time for STOP condition
Bus free time between STOP and START
condition
20 +
0.1 C B
20 +
0.1 C B
0.6
1.3
300
300
ns
ns
m s
m s
15. The maximum number of connected I 2 C devices is dependent on the number of available addresses and the maximum bus capacitance
to still guarantee the rise and fall times of the bus signals.
16. An I 2 C device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V IHmin of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
17. The maximum t HD,DAT has only to be met if the device does not stretch the LOW period (t LOW ) of the SCL signal.
18. A Fast ? mode I 2 C ? bus device can be used in a standard ? mode I 2 C bus system, but the requirement t SU,DATA w 250 ns must than be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line trmax + t SU,DATA = 1000 + 250 = 1250 ns (according to the
standard ? mode I 2 C ? bus specification) before the SCL line is released.
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