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参数资料
| 型号： | AN1607 |
| 厂商： | Motorola, Inc. |
| 英文描述： | ITC122 low voltage micro to motor interface |
| 中文描述： | ITC122的低电压微电机接口 |
| 文件页数： | 7/12页 |
| 文件大小： | 227K |
| 代理商： | AN1607 |
7
MOTOROLA
Phase Voltage Feedback:
Phase voltage feedback signals Pa, Pb, & Pc are also
included on feedback connector J2. They are located on pins
2, 4, and 6. These pins provide motor phase voltages divided
down with the same 50 mV/Volt ratio as Vbus. They are also
unfiltered and unbuffered signals.
APPLICATION EXAMPLE
An application example shown in Figure 5 illustrates system
connections to an ASB124 control board and a Brushless DC
motor. This arrangement can be run stand alone, or the
ASB124 can be connected to an MMDS05 for code
development. The two boards are designed such that the
Drive and Feedback ribbon connectors line up. Ribbon cables
are supplied with the ASB124 board. Once they are plugged
in it is only a matter of connecting power supply, motor, and
Hall sensor leads to get a system up and running.
Figure 5. Application Example
MOTION CONTROL DEVELOPMENT BOARD
LOW VOLTAGE
MICRO TO MOTOR INTERFACE
7.5–28 VDC
DRIVE
FEEDBACK
MOTOROLA
ASB124
MOTOROLA
ITC122
BRUSHLESS MOTOR
12–48 VDC
Aout
Bout
Cout
B+
GND
GND
GND
B+
H
H
H
G
+
An important application’s consideration is pulse width
modulation topology. The controller that is shown in Figure 5
pulse width modulates Atop, Btop, & Ctop inputs, and
commutates Abot, Bbot, & Cbot. This configuration performs
better from a power dissipation standpoint than its more
commonly used alternative, namely lower half bridge pulse
width modulation with upper half bridge commutation. When
the upper half bridge is pulse width modulated, circulating
currents flow through the lower rds(on) and lower forward
diode voltages of the N–Channel transistors. Since transition
times for both P–Channel & N–Channel transistors are
approximately the same, high side pulse width modulation is
considerably more efficient. With more efficient operation,
available output power to the motor is maximized.
DESIGN CONSIDERATIONS
A block diagram that provides an overview of the design is
illustrated in Figure 6. Top and Bottom inputs for each phase
are coupled to gate drive circuits through cross coupled NOR
gates. This arrangement locks out the bottom input when both
inputs for one phase are low, thereby adding robustness for
lab use. If all six inputs are low, transistors Atop, Btop, and
Ctop are turned on, which brakes the motor. This condition can
occur when an ASB124 controller is powered down.
The output is a 3 phase bridge that is made from
complimentary 30 amp surface mount MOSFET’s. Gate drive
for the N–Channel transistors is provided by MC33152
MOSFET drivers and for the P–Channels by a discrete circuit.
A more detailed view of the gate drive circuits is shown in
Figure 7. Both the P–Channel & N–Channel transistors have
transition times targeted for approximately 200 nsec. This
target allows high enough value gate drive resistors to
somewhat soften diode snap, yet produces switching losses
that are less than static losses at 23 KHz.
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