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参数资料
| 型号： | AN1672 |
| 厂商： | ON SEMICONDUCTOR |
| 英文描述： | The ECL Translator Guide |
| 中文描述： | 翻译的ECL指南 |
| 文件页数： | 8/10页 |
| 文件大小： | 64K |
| 代理商： | AN1672 |
AN1672/D
http://onsemi.com
8
Section 3: Translation from Non ECL Drivers to Different ECL Operating Mode Receivers
Table 9. Translation from Non ECL Drivers to Different ECL Operating Mode Receivers
To:
From:
PECL
V
CC
= +5 V
LVPECL
V
CC
= +2.5 V
LVPECL
V
CC
= +3.3 V
LVNECL
V
EE
= 3.3 V
NECL
V
EE
= 4.5 to 5.2 V
TTL
H351
H606
ELT20
ELT22
ELT28*
ELT20, or
ELT22, + LVEL92;
if V
is limited to
V
CC
= 3.3 V use EPT20,
EPT22, or LVELT22
ELT20 or
ELT22 + LVEL91
H424
H124
H600
H602
H604
ELT24
LVTTL/LVCMOS/
HSTL/CML/LVDS
V
CC
= 2.5 V
NB100LVEP91
NB100LVEP91
NB100LVEP91
LVTTL/LVCMOS
V
CC
= 3.3 V
H351
H606
ELT20
ELT22
ELT28*
OR:
(EPT20 or EPT22 or EP24
or LVELT22) + 5 V PECL
line receiver
EPT20
EPT22
LVELT22
MC100EPT622
EPT24 or
NB100LVEP91
NB100LVEP91 or
EPT24 + EL91
CMOS
V
DD
= +5 V
H352
ELT20
ELT22
ELT28
H352
+
LVEL92
H352
+
LVEL91
H352
+
EL91
*Bidirectional
From TTL to PECL
An open, floating TTL input will drift to near V
CC
and
may inject noise into the device under this condition. It is
recommended to tie any unused TTL input to V
CC
.
MC10H351 as TTL to PECL
The MC10H351 operates over the frequency range from
DC to >200 MHz. Although operation to higher frequencies
is possible, the output V
OH
levels will decrease, rolling off
as frequency increases. TTL V
CC
(Pin 11) would best be
connected to the TTL logic devices positive supply, while
ECL V
CC
is recommended to be isolated to a separate PECL
logic plane, if possible. V
EE
, Pin 8, may be connected to the
common ground plane.
An open, floating TTL input (Pins 7, 8, 9, 12, 14) will drift
to near V
CC
and considerations must be taken to reduce
noise injected into the device under this condition, such as
connecting unused inputs to V
CC
. The Common Strobe pin
is TTL type input.
Output to output skew is 150 ps worst case (at +70
°
C).
Device to Device slew is less than 300 ps skew. Jitter is 40
to 60 ps.
MC10H606 / MC100H606 as TTL to PECL
This device offers translation and registration
(reclocking) of TTL signals to PECL. Special advantages
may be realized with this device, consult the device data
sheets for specific features.
MC10ELT20 / MC100ELT20 and MC10ELT22 /
MC100ELT22 as TTL to PECL
These devices do not sport any internal input resistor
network to force a default level on an open floating pin. An
open, floating TTL input (Pins 7, 8, 9, 12, 14) will drift to
near V
CC
and considerations must be taken to reduce noise
injected into the device under this condition, such as
connecting unused inputs to V
CC
.
Higher operating frequency range will be affected by
input swing; a higher input swing will allow a higher
operating range.
From TTL to LVPECL
Translation from TTL to LVPECL requires a twostage
process: first TTL to PECL (with a 5 V supply) second
PECL to LVPECL. The first may be accomplished per the
segment above on TTL to PECL. The second stage is done
with MC100LVEL92 (see also PECL to LVPECL segment).
Under the condition where the TTL signal is confined to
not exceed 3.3 V, a MC10EPT20 / MC100EPT20,
MC10EPT22 / MC100EPT22, or MC100LVELT22 may be
used. The MC100LVELT22 has operation frequency band
range from <1 Hz (with sufficiently sharp edges) to
600 MHz. Diode clamping may be used to prevent input
signals from exceeding 3.3 V
CC
.
From TTL to LVNECL
Translation from TTL to LVNECL is done in two stages:
1. Use TTL to PECL (ELT20 or ELT22)
2. Then use PECL to LVNECL Translation (LVEL91).
Both are described above. Alternatively, the first
translation may be TTL to LVPECL and the second
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