参数资料
| 型号： | AP1539SDPG-13 |
| 厂商： | Diodes Inc |
| 文件页数： | 9/13页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 4A 8SOIC |
| 产品变化通告： | Copper Bond Wire Change 13/Jan/2012 |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 18 V |
| 输入电压： | 3.6 V ~ 18 V |
| 频率 - 开关： | 300kHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 无 |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOP |
| 产品目录页面： | 1136 (CN2011-ZH PDF) |
| 其它名称： | AP1539SDPGDIDKR |
AP1539
18V 4A 300KHz BUCK CONVERTER
Functional Descriptions
PWM Control
The AP1539 is a DC/DC converter that employs pulse width
modulation (PWM) scheme. Its pulse width varies in the range of
0% to 99%, based on the output current loading. The output
ripple voltage caused by the PWM high frequency switching can
Inductor Selection
For most designs, the operates with inductors of 22μH to
33μH. The inductor value can be derived from the following
equation:
× OUT
easily be reduced through an output filter. Therefore, this
converter provides a low ripple output supply over a broad range
of input voltage & output current loading
L =
V IN ? V OUT
fs × Δ I
V
V IN
I PEAK > I OUT(MAX) + 2
Under Voltage Lockout
The under voltage lockout circuit of the AP1539 assures that the
high-side MOSFET driver remains in the off state whenever the
supply voltage drops below 3.3V. Normal operation resumes
once V CC rises above 3.5V.
Current Limit Protection
The current limit threshold is set by external resistor R OCSET
connected from V CC supply to OCSET pin. The internal sink
current I OCSET (90uA typical) across this resistor sets the voltage
at OCSET pin. When the PWM voltage is less than the voltage at
OCSET, an over-current condition is triggered.
The current limit threshold is given by the following equation:
I PEAK × R DS(ON) = I OCSET × R OCSET
( Δ I )
where,
Where Δ I L is inductor Ripple Current. Large value inductors lower
ripple current and small value inductors result in high ripple
current. Choose inductor ripple current approximately 15% of the
maximum load current 4A, ? I L =0.6A. The DC current rating of the
inductor should be at least equal to the maximum load current
plus half the ripple current to prevent core saturation (4A+0.3A).
Input Capacitor Selection
This capacitor should be located close to the IC using short leads
and the voltage rating should be approximately 1.5 times the
maximum input voltage. The RMS current rating requirement for
the input capacitor of a buck regulator is approximately 1 ? 2 the
DC load current. A low ESR input capacitor sized for maximum
RMS current must be used. A 470μF low ESR capacitor for most
applications is sufficient.
Output Capacitor Selection
The output capacitor is required to filter the output voltage and
provides regulator loop stability. The important capacitor
parameters are the 100KHz Equivalent Series Resistance (ESR),
the RMS ripples current rating, voltage rating and capacitance
value. For the output capacitor, the ESR value is the most
important parameter. The output ripple can be calculated from
the following formula.
× OUT
Δ I =
V IN ? V OUT
fs × L
V
V IN
V RIPPLE = ΔI L × ESR
The bulk capacitor’s ESR will determine the output ripple voltage
I PEAK is the output peak current; R DS (ON) is the MOSFET ON
resistance; F S is the PWM frequency (300KHz typical). Also, the
inductor value will affect the ripple current Δ I.
The above equation is recommended for input voltage range of
5V to 18V. For input voltage lower than 5V, higher than 18V or
ambient temperature over 100°C, higher R OCSET is
recommended.
The recommended minimum R OCSET value is summarized below:
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to the
capacitance and its voltage rating. In most case, higher voltage
electrolytic capacitors have lower ESR values. Most of the time,
capacitors with much higher voltage ratings may be needed to
provide the low ESR values required for low output ripple voltage.
PCB Layout Guide
If you need low T C & T J or large PD (Power Dissipation), The dual
SW pins(5& 6) and Vss pins(7& 8)on the SOP-8L package are
V OUT
(V)
0.8
1.0
1.2
1.8
2.5
3.3
5.0
5V
6.8K
6.8K
6.8K
6.8K
6.8K
6.8K
N/A
V IN (V)
12V
3.9K
3.9K
3.9K
3.9K
3.9K
3.9K
3.9K
18V
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
5.6K
internally connected to die pad, The evaluation board should be
allowed for maximum copper area at output (SW) pins.
1. Connect FB circuits (R 1 , R 2 , C 1 ) as closely as possible and
keep away from inductor flux for pure V FB .
2. Connect C3 to Vcc and Vss pin as closely as possible to get
good power filter effect.
3. Connect R4 to Vcc and OCSET pin as closely as possible.
4. Connect ground side of the C2 & D1 & C4 as closely as
possible and use ground plane for best performance.
AP1539 Rev. 4
DS31477
9 of 13
OCTOBER 2009
? Diodes Incorporated
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