参数资料
| 型号： | AP7115-35WG-7 |
| 厂商： | Diodes Inc |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3.5V .15A SOT-25 |
| 标准包装： | 3,000 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3.5V |
| 输入电压： | 最高 5.5V |
| 电压 - 压降（标准）： | 0.2V @ 150mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 150mA（最小值） |
| 电流 - 限制（最小）： | 200mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SC-74A，SOT-753 |
| 供应商设备封装： | SOT-25 |
| 包装： | 带卷 (TR) |
AP7115
150mA LOW DROPOUT LINEAR REGULATOR WITH
SHUTDOWN
Application Note
Input Capacitor
An 1uF input capacitor is required between the AP7115 input pin
and GND.
There are no requirements for the ESR on input capacitor, but
tolerance and temperature coefficient must be considered.
Output Capacitor
The AP7115 can work with very small ceramic output capacitors
(1uF or greater). Higher capacitance values help to improve
transient. The output capacitor’s ESR is critical because it from a
zero to provide phase lead which is required for loop stability.
Figure below is Cout ESR vs. Load Current.
AP7115 Region of Stable Cout ESR vs.
Load Current
100
10
1
PCB Layout
Optimum performance can only be achieved when the device is
mounted on a PC board according to the diagram below:
0.1
Stable
Thermal Considerations
Thermal Shutdown Protection limits power dissipation in AP7115.
When the operation junction temperature exceeds 155°C, the
0.01
0
20
40
60
80
100
120
140
160
Over Temperature Protection circuit starts the thermal shutdown
function and turns the pass element off. The pass element turn
on again after the junction temperature cools by 30°C. For
Load Current (mA)
Band-Gap Bypass Capacitor
0.1uF bypass capacitor Between BP pin and GND can reduces
output voltage noise.
Shutdown Input Operation
The AP7115 is shutdown by pulling the EN pin low, and turned on
by driving the input high. If the shutdown feature is not required,
the EN pin should be tied to VIN to keep the regulator on at all
times.
Dropout Voltage
V DROPOUT ＝ V IN － V OUT ＝ R DS(ON) ×I OUT
continuous operation, do not exceed absolute maximum
operation junction temperature 125°C. The power dissipation
definition in device is:
P D = (V IN ? V OUT ) x I OUT + V IN x I Q
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of surroundings
airflow and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by the
following formula:
P D(MAX) = ( T J(MAX) - T A ) / θ JA
Where T J(MAX) is the maximum operation junction temperature
125°C, T A is the ambient temperature and the θ JA is the junction
to ambient thermal resistance.
Current Limit
The AP7115 monitors and controls the PMOS’ gate voltage,
limiting the output current to 250mA(typ.). The output can be
shorted to ground for an indefinite period of time without
damaging the part.
AP7115 Rev. 10
8 of 11
MAY 2009
? Diodes Incorporated
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