参数资料
| 型号： | AP7173-FNG-7 |
| 厂商： | Diodes Inc |
| 文件页数： | 5/15页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 1.5A 10DFN |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.8 V ~ 3.3 V |
| 输入电压： | 1 V ~ 5.5 V |
| 电压 - 压降（标准）： | 0.165V @ 1.5A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 1.5A（最小值） |
| 电流 - 限制（最小）： | 2A |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-UFDFN 裸露焊盘 |
| 供应商设备封装： | DFN3030-10 |
| 包装： | 标准包装 |
| 其它名称： | AP7173-FNG-7DIDKR |
AP7173
1.5A LOW DROPOUT LINEAR REGULATOR WITH
PROGRAMMABLE SOFT-START
Electrical Characteristics
At V EN = 1.1V, V IN = V OUT + 0.5V, C VCC = 0.1uF, C IN = C OUT = 10uF, I OUT = 50mA, V VCC = 5.0V, and T A = –40°C to +85°C,
unless otherwise noted. Typical values are at T A = +25°C.
Symbol
Parameter
Test Conditions
Min
Typ.
Max
Unit
V IN
Input Voltage Range
V OUT + V DO
5.5 V
V VCC
Bias Pin Voltage Range
(Note 7)
2.7 5.5 V
V REF
Internal Reference
(Adj.)
T A = +25 oC
0.792 0.8 0.808 V
Output Voltage Range V IN = 5V, I OUT = 1.5A
0.8 3.3 V
V OUT
Accuracy (Note 8)
2.97V ≤ V VCC ≤ 5.5V,
50mA ≤ I OUT ≤ 1.5A
–2 ±0.5 2 %
Δ V OUT / Δ V IN /
V OUT
Line Regulation V OUT (NOM) + 0.5 ≤ V IN , ? 5.5V
0.03 %/V
Δ V OUT /V OUT
/ Δ I OUT
Load Regulation 50mA ≤ I OUT ≤ 1.5A
0.09
%/A
V DO
Dropout Voltage
(Note 9)
I OUT = 1.5A , V VCC –V OUT(NOM) ≥ 3.25V
I OUT = 1.5A, V IN = V VCC
165
1.5
270 mV
1.7 V
I CL
Current Limit V OUT = 80% x V OUT (NOM)
2 3
4 A
I SHORT
I VCC
Short-Circuit Current V OUT < 0.2V
Bias Pin Current
0.6 1 A
1 2 mA
I SHDN
Shutdown Supply
Current (I GND )
V EN ≤ 0.4V
1
50
μA
I FB
Feedback Pin Current
–1 0.1 1 μA
PSRR
1KHz, I OUT = 1A,
Power-Supply Rejection V IN = 1.8V, V OUT = 1.5V
(V IN to V OUT ) 300KHz, I OUT =1A,
V IN = 1.8V, V OUT =1.5V
1KHz, I OUT = 1A,
Power-SupplyRejection VI N = 1.8V, V OUT =1.5V
(V VCC to V OUT ) 300KHz, I OUT = 1A,
V IN = 1.8V, V OUT =1.5V
60
30
50
30
dB
dB
T ST
Startup Time R LOAD for I OUT = 1.0A, C SS = open 100 μS
I SS
Soft-Start Charging
Current
V SS = 0.4V
440 nA
V EN, HI
V EN, LO
V EN, HYS
I EN
V PG, TH
V PG, HYS
V PG, LO
Enable Input High Level
Enable Input Low Level
Enable Pin Hysteresis
Enable Pin Current V EN = 5V
PG Trip Threshold V OUT decreasing
PG Trip Hysteresis
PG Output Low Voltage I PG = 1mA (sinking), V OUT <V PG , TH
1.1 5.5 V
0 0.4 V
50 mV
0.1 1 μA
85 90 94 %V OUT
3 %V OUT
0.3 V
I PG, LKG
PG Leakage Current V PG = 5.25V, V OUT >V PG , TH
0.1
1 μA
T SD
Thermal Shutdown
Temperature
Shutdown, temperature increasing +150
Reset, temperature decreasing +130
oC
θ JA
Thermal Resistance
Junction-to-Ambient
DFN3030-10 (Note 10)
SO-8EP (Note 11)
35
23
o
C/W
θ JC
Thermal Resistance
Junction-to-Case
DFN3030-10 (Note 10) 4.9
SO-8EP (Note 11) 1.8
o
C/W
Notes:
7. V VCC should be higher or equal to V IN in this chip.
8. Tested at 0.8V; resistor tolerance is not taken into account.
9. Dropout is defined as the voltage from V IN to V OUT when V OUT is 3% below nominal.
10. Test condition for DFN3030-10: Device mounted on FR-4 substrate (2s2p), 2"*2" PCB, with 2oz copper trace thickness and large pad pattern.
11. Test condition for SOP-8L-EP: Device mounted on FR-4 substrate (2s2p), 2"*2" PCB, with 2oz copper trace thickness and large pad pattern.
AP7173
Document number: DS31369 Rev. 9 - 2
5 of 15
April 2011
? Diodes Incorporated
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