October 2003
i
2003 Actel Corporation
ProASICPLUS Flash Family FPGAs
Features and Benefits
High Capacity
75,000 to 1 million System Gates
27k to 198kbits of Two-Port SRAM
66 to 712 User I/Os
Reprogrammable Flash Technology
0.22
4LM Flash-based CMOS Process
Live at Power-Up, Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Power-Up Cycles
Performance
3.3V, 32-bit PCI (up to 50 MHz)
Two Integrated PLLs
External System Performance up to 150 MHz
Secure Programming
The Industry’s Most Effective Security Key (FlashLock
)
Prevents Read Back of Programming Bitstream
Low Power
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
High Performance Routing Hierarchy
Ultra-Fast Local and Long-Line Network
High Speed Very Long-Line Network
High Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
I/O
Schmitt-Trigger Option on Every Input
2.5V/3.3V Support with Individually-Selectable Voltage and
Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin Compatible Packages across ProASICPLUS Family
Unique Clock Conditioning Circuitry
PLL with Flexible Phase, Multiply/Divide and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Standard FPGA and ASIC Design Flow
Flexibility with Choice of Industry-Standard Frontend Tools
Efficient Design through Frontend Timing and Gate Optimization
ISP Support
In-System Programming (ISP) via JTAG Port
SRAMs and FIFOs
ACTgen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
TM
Table 1 ProASICPLUS Product Profile
Device
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
Maximum System Gates
75,000
150,000
300,000
450,000
600,000
750,000
1,000,000
Maximum Tiles (Registers)
3,072
6,144
8,192
12,288
21,504
32,768
56,320
Embedded RAM Bits (k=1,024
bits)
27k
36k
72k
108k
126k
144k
198k
Embedded RAM Blocks (256x9)
12
16
32
48
56
64
88
LVPECL
22
2
PLL
22
2
Global Networks
44
4
Maximum Clocks
24
32
48
56
64
88
Maximum User I/Os
158
242
290
344
454
562
712
JTAG ISP
Yes
PCI
Yes
Package (by pin count)
TQFP
100, 144
100
–
PQFP
208
PBGA
–
456
FBGA
144
144, 256
144, 256, 484 256, 484, 676
676, 896
896, 1152
v3.3