参数资料
| 型号： | APA150-PQG208A |
| 厂商： | Microsemi SoC |
| 文件页数： | 161/178页 |
| 文件大小： | 0K |
| 描述： | IC FPGA PROASIC+ 150K 208-PQFP |
| 标准包装： | 24 |
| 系列： | ProASICPLUS |
| RAM 位总计： | 36864 |
| 输入/输出数： | 158 |
| 门数： | 150000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页当前第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页
ProASICPLUS Flash Family FPGAs
v5.9
2-73
Pin Description
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible
with
standard
LVTTL
and
LVCMOS
specifications. Unused I/O pins are configured as inputs
with pull-up resistors.
NC
No Connect
To maintain compatibility with other Actel ProASICPLUS
products, it is recommended that this pin not be
connected to the circuitry on the board.
GL
Global Pin
Low skew input pin for clock or other global signals. This
pin can be configured with an internal pull-up resistor.
When it is not connected to the global network or the
clock conditioning circuit, it can be configured and used
as a normal I/O.
GLMX
Global Multiplexing Pin
Low skew input pin for clock or other global signals. This
pin can be used in one of two special ways (refer to
Actel’s Using ProASICPLUS Clock Conditioning Circuits).
When the external feedback option is selected for the
PLL block, this pin is routed as the external feedback
source to the clock conditioning circuit.
In applications where two different signals access the
same global net at different times through the use of
GLMXx and GLMXLx macros, this pin will be fixed as one
of the source pins.
This pin can be configured with an internal pull-up
resistor. When it is not connected to the global network
or the clock conditioning circuit, it can be configured and
used as any normal I/O. If not used, the GLMXx pin will
be configured as an input with pull-up.
Dedicated Pins
GND
Ground
Common ground supply voltage.
VDD
Logic Array Power Supply Pin
2.5 V supply voltage.
VDDP
I/O Pad Power Supply Pin
2.5 V or 3.3 V supply voltage.
TMS
Test Mode Select
The TMS pin controls the use of boundary-scan circuitry.
This pin has an internal pull-up resistor.
TCK
Test Clock
Clock input pin for boundary scan (maximum 10 MHz). Actel
recommends adding a nominal 20 k
Ω pull-up resistor to this
pin.
TDI
Test Data In
Serial input for boundary scan. A dedicated pull-up
resistor is included to pull this pin high when not being
driven.
TDO
Test Data Out
Serial output for boundary scan. Actel recommends
adding a nominal 20k
Ω pull-up resistor to this pin.
TRST
Test Reset Input
Asynchronous,
active
low
input pin
for
resetting
boundary-scan circuitry. This pin has an internal pull-up
resistor. For more information, please refer to Power-up
Behavior of ProASICPLUS Devices application note.
Special Function Pins
RCK
Running Clock
A free running clock is needed during programming if
the programmer cannot guarantee that TCK will be
uninterrupted. If not used, this pin has an internal pull-
up and can be left floating.
NPECL
User Negative Input
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
PPECL
User Positive Input
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
AVDD
PLL Power Supply
Analog VDD should be VDD (core voltage) 2.5 V (nominal)
and be decoupled from GND with suitable decoupling
capacitors to reduce noise. For more information, refer
to Actel’s Using ProASICPLUS Clock Conditioning Circuits
application note. If the clock conditioning circuitry is not
used in a design, AVDD can either be left floating or tied
to 2.5 V.
AGND
PLL Power Ground
The analog ground can be connected to the system
ground. For more information, refer to Actel’s Using
ProASICPLUS Clock Conditioning Circuits application note.
If the PLLs or clock conditioning circuitry are not used in
a design, AGND should be tied to GND.
相关PDF资料 |
PDF描述 |
|---|---|
| ABM43DTBS | CONN EDGECARD 86POS R/A .156 SLD |
| APA150-PQ208A | IC FPGA PROASIC+ 150K 208-PQFP |
| ABM43DTAS | CONN EDGECARD 86POS R/A .156 SLD |
| EP4CGX22BF14I7N | IC CYCLONE IV GX FPGA 22K 169FBG |
| ACC43DRTN-S93 | CONN EDGECARD 86POS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| APA150-PQG208I | 功能描述:IC FPGA PROASIC+ 150K 208-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| APA150-PQGB | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA150-PQGES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA150-PQGI | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA150-PQGM | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
发布紧急采购，3分钟左右您将得到回复。