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参数资料
| 型号： | APE2901N-50 |
| 厂商： | ADVANCED POWER ELECTRONICS CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, 150 kHz SWITCHING FREQ-MAX, PDSO3 |
| 封装： | LEAD FREE, SOT-23, 3 PIN |
| 文件页数： | 9/10页 |
| 文件大小： | 364K |
| 代理商： | APE2901N-50 |
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
OPERATING MODES:
Caremustbetakentoassurethattheappropriateflagismonitoredbyeach
system (i.e.
FF is monitored on the device where Wis used; EFis monitored
on the device where
Ris used). For additional information, refer to Tech Note
8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note
6: Designing with FIFOs.
SINGLE DEVICE MODE
A single IDT72V01/72V02/72V03/72V04/72V05/72V06 may be used
when the application requirements are for 512/1,024/2,048/4,096/8,192/
16,384wordsorless.ThesedevicesareinaSingleDeviceConfigurationwhen
the Expansion In (
XI) control input is grounded (see Figure 12).
TheseFIFOscaneasilybeadaptedtoapplicationswhentherequirements
are for greater than 512/1,024/2,048/4,096/8,192/16,384 words. Figure 14
demonstratesDepthExpansionusingthreeIDT72V01/72V02/72V03/72V04/
72V05/72V06s. Any depth can be attained by adding additional IDT72V01/
72V02/72V03/72V04/72V05/72V06s. These devices operate in the Depth
Expansion mode when the following conditions are met:
1. ThefirstdevicemustbedesignatedbygroundingtheFirstLoad(
FL)control
input.
2. All other devices must have
FLin the HIGH state.
3. The Expansion Out (
XO)pinofeachdevicemustbetiedtotheExpansion
In (
XI ) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag (
FF)andEmpty
Flag (
EF). This requires the ORing of all EFs and ORing of all FFs (i.e.
all must be set to generate the correct composite
FForEF). SeeFigure14.
5. The Retransmit (
RT) function and Half-Full Flag ( HF) are not available
in the Depth Expansion Mode.
For additional information, refer to Tech Note 9: Cascading FIFOs or FIFO
Modules.
USAGE MODES:
WIDTH EXPANSION
Wordwidthmaybeincreasedsimplybyconnectingthecorrespondinginput
controlsignalsofmultipledevices. Statusflags(
EF,FFandHF)canbedetected
from any one device. Figure 13 demonstrates an 18-bit word width by using
two IDT72V01/72V02/72V03/72V04/72V05/72V06s. Any word width can be
attainedbyaddingadditionalIDT72V01/72V02/72V03/72V04/72V05/72V06s
(Figure 13).
BIDIRECTIONAL OPERATION
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT72V01/72V02/72V03/72V04/72V05/72V06s as shown in Figure 16. Both
Depth Expansion and Width Expansion may be used in this mode.
DATA FLOW-THROUGH
Two types of flow-through modes are permitted, a read flow-through and
writeflow-throughmode. Forthereadflow-throughmode(Figure17),theFIFO
permits a reading of a single word after writing one word of data into an empty
FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of
W,calledthefirstwriteedge,anditremainsonthebusuntilthe Rlineisraised
from LOW-to-HIGH, after which the bus would go into a three-state mode after
tRHZ ns. The
EFline would have a pulse showing temporary deassertion and
then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permits the writing of
asinglewordofdataimmediatelyafterreadingonewordofdatafromafullFIFO.
The
Rline causes the FFto be deasserted but the Wline being LOW causes
it to be asserted again in anticipation of a new data word. On the rising edge
of
W,thenewwordisloadedintheFIFO.TheWlinemustbetoggledwhenFF
is not asserted to write new data in the FIFO and to increment the write pointer.
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