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参数资料
| 型号： | APL5912-KAC-TR |
| 厂商： | Anpec Electronics Corporation |
| 英文描述： | 0.8V Reference Ultra Low Dropout (0.2V@5A) Linear Regulator |
| 中文描述： | 0.8V的参考超低压降（0.2V的@ 5A）条线性稳压器 |
| 文件页数： | 14/20页 |
| 文件大小： | 477K |
| 代理商： | APL5912-KAC-TR |
Copyright
ANPEC Electronics Corp.
Rev. A.6 - Jun., 2005
APL5912
www.anpec.com.tw
14
Application Information (Cont.)
the calculated C1.
- The C1 calculated from equation (4) must meet
the following equation :
50
1
5.1
C1
(m
Where R1=R1
(calculated)
from equation (3)
If the C1
(calculated)
can not meet the equation (5),
please use the Condition 3.
- Use equation (2) to calculate the R2.
Condition 3: Low ESR (eg. Ceramic Capacitors)
- Calculate the R1 as the following:
294)
ESR
(5.9
R1
)
(m
)
(k
+
=
Select a proper R1
(selected)
to be a little larger than
the calculated R1.
The minimum selected R1
is equal to 1k
when the calculated R1 is
smaller than 1k or negative.
- Calculate the C1 as the following :
Where R1=R1
(selected)
Select a proper C1
(selected)
to be a little smaller
than the calculated C1.
- The C1 calculated from equation (7) must meet
the following equation :
V
1.25
0.033
C1
(k
Where R1=R1
(calculated)
from equation (6)
If the C1
(calculated)
can not meet the equation (8),
please use the Condition 2.
- Use equation (2) to calculate the R2.
The reason to have three conditions described above
is to optimize the load transient responses for all kinds
of the output capacitor. For stability only, the Condition
2, regardless of equation (5), is enough for all kinds of
output capacitor.
Feedback Network (Cont.)
(5)
R1
V
37.5
1
ESR
)
(k
OUT(V)
)
(pF)
+
≥
(6)
V
37.5
C
OUT(V)
OUT(uF)
(7)
R1
V
37.5
1
C
8.5)
ESR
(0.17
C1
)
(k
OUT(V)
OUT(uF)
)
(m
(pF)
+
+
=
(8)
C
ESR
R1
OUT(uF)
)
(m
OUT(V)
(pF)
+
≥
PCB Layout Considerations (See Figure 2)
1. Please solder the Exposed Pad and VIN together
on the PCB. The main current flow is through the
exposed pad. The role of VIN is a voltage sense.
Refer Figure 3 to make a proximate topology.
2. Please place the input capacitors for VIN and VCNTL
pins near pins as close as possible.
3. Ceramic decoupling capacitors for load must be
placed near the load as close as possible.
4. To place APL5912 and output capacitors near the
load is good for performance.
5. The negative pins of the input and output capacitors
and the GND pin of the APL5912 are connected to
the ground plane of the load.
6. Please connect PIN 3 and 4 together by a wide
track or plane on the Top layer.
7. Large current paths must have wide tracks.
8. See the Typical Application
- Connect the one pin of the R2 to the GND of
APL5912.
V
CNTL
V
OUT
C
CNTL
V
IN
GND
VOUT
VCNTL
VIN
C
IN
C
OUT
APL5912
R1
C1
VOUT
FB
R2
Load
Figure 2
- Connect the one pin of R1 to the Pin 3 of APL5912
- Connect the one pin of C1 to the Pin 3 of APL5912
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