参数资料
型号: APT55M85LFLLG
厂商: MICROSEMI POWER PRODUCTS GROUP
元件分类: JFETs
英文描述: 59 A, 550 V, 0.085 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-264AA
封装: TO-264, 3 PIN
文件页数: 2/4页
文件大小: 70K
代理商: APT55M85LFLLG
Note:
Duty Factor D =
t1/t
2
Peak TJ = PDM x ZθJC + TC
t1
t2
P
DM
SINGLE PULSE
Z
θJC
,THERMAL
IMPEDANCE
(°C/W)
10-5
10-4
10-3
10-2
10-1
1.0
RECTANGULARPULSEDURATION(SECONDS)
FIGURE 1, MAXIMUM EFFECTIVE TRANSIENT THERMAL IMPEDANCE, JUNCTION-TO-CASE vs PULSE DURATION
0.20
0.16
0.12
0.8
0.04
0
0.5
0.1
0.3
0.7
0.9
0.05
050-7231
Rev
A
3-2003
DYNAMIC CHARACTERISTICS
APT55M85 B2FLL - LFLL
1 Repetitive Rating: Pulse width limited by maximum junction
temperature
2 Pulse Test: Pulse width < 380 s, Duty Cycle < 2%
3 See MIL-STD-750 Method 3471
APT Reserves the right to change, without notice, the specifications and information contained herein.
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Characteristic / Test Conditions
Continuous Source Current (Body Diode)
Pulsed Source Current 1 (Body Diode)
Diode Forward Voltage 2 (VGS = 0V, IS = -59A)
Peak Diode Recovery dv/dt 5
Reverse Recovery Time
(IS = -59A, di/dt = 100A/s)
Reverse Recovery Charge
(IS = -59A, di/dt = 100A/s)
Peak Recovery Current
(IS = -59A, di/dt = 100A/s)
Symbol
IS
ISM
VSD
dv/
dt
trr
Qrr
IRRM
UNIT
Amps
Volts
V/ns
ns
C
Amps
Symbol
Ciss
Coss
Crss
Qg
Qgs
Qgd
td(on)
t r
td(off)
tf
Characteristic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge 3
Gate-Source Charge
Gate-Drain ("Miller ") Charge
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Test Conditions
VGS = 0V
VDS = 25V
f = 1 MHz
VGS = 10V
VDD = 275V
ID = 59A @ 25°C
VGS = 15V
VDD = 275V
ID = 59A @ 25°C
RG = 0.6
MIN
TYP
MAX
6590
1296
91
157
38
86
19
14
41
6
UNIT
pF
nC
ns
MIN
TYP
MAX
59
236
1.3
15
Tj = 25°C
270
Tj = 125°C
540
Tj = 25°C
1.8
Tj = 125°C
6.2
Tj = 25°C
16
Tj = 125°C
29
THERMAL CHARACTERISTICS
Symbol
RθJC
RθJA
MIN
TYP
MAX
0.18
40
UNIT
°C/W
Characteristic
Junction to Case
Junction to Ambient
4 Starting Tj = +25°C, L = 1.72mH, RG = 25, Peak IL = 59A
5 dv
/dt numbers reflect the limitations of the test circuit rather than the
device itself. I
S
-I
D
59A di
/dt ≤ 700A/s V
R
V
DSS
T
J
150
°C
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