www.anpec.com.tw
5
APW 7045
Copyright
ANPEC Electronics Corp.
Rev.A.5 - Jan., 2003
RT-1
R
DS(ON)
Functional Pin Description ( Cont.)
PGOOD (Pin 3)
PGOOD is an open collector output used to indicate
the status of the output voltages. This pin is pulled
low when the synchronous regulator output is not within
±10% of the DAC reference voltage or linear regula-
tor output is below under-voltage threshold.
SD (Pin 4)
The pin shuts down all the outputs. A TLL-compatible
, logic level high signal applied at this pin immediately
discharges the soft-start capacitor , disabling all the
outputs . Left open , this pin is pulled low by an inter-
nal pull-down resistor , enabling operation.
FB2 (Pin 5)
Connect this pin to a resistor divider to set the linear
regulator output voltage (V
MEM
). The output voltage
set by the resistor divider is determined using the
following formula :
V
MEM
= 1.5V x (1 + R
Where R
OUT
is the resistor connected from V
MEM
to
FB2, and R
GND
is the resistor connected from FB2 to
ground. The voltage at this pin is also monitored for
Under-Voltage protection.
SS (Pin 6)
Connect a capacitor from this pin to ground. This
capacitor , along with an internal 28uA current source
, sets the soft-start interval of the converter.
FAULT (Pin 7)
This pin provides oscillator switching frequency
adjustment, referring to the typical performence. By
placing a resistor (RT, k
) from this pin to GND, the
nominal 200kHz switching frequency is increased
according to the following equation :
Fs =200 +4000
x (1.16 -1.4
RT
(R
T
to GND, R
T
≥
10k
is more accurate)
Conversely, connecting a resistor from this pin to +12V
reduces the switching frequency according to the
following equation :
Fs =200 + 47920
(R
T
to 12V, R
T
≥
250 k
is more accurate)
Nominally, the voltage at this pin is 1.26V. In the event
of an over-voltage or over-current condition, this pin
is internally pulled to VCC.
GND (Pin 8)
Signal ground for the IC. All voltage levels are
measured with respect to this pin.
COMP and FB1 (Pin 9, and 10)
COMP and FB1 are the available external pins of the
PWM converter error amplifier. The FB1 pin is the
inverting input of the error amplifier. Similarly , the
COMP pin is the error amplifier output. These pins are
used to compensate the voltage-mode control feed-
back loop of the synchronous PWM converter.
VSEN1 (Pin 11)
This pin is connected to the PWM converter’s output
voltage. The PGOOD and OVP comparator circuits
use this signal to report output voltage status and for
over- voltage protection.
OCSET (Pin 12)
Connect a resistor (R
OCSET
) from this pin to the drain
of PWM converter’s upper MOSFET. R
OCSET
, an in-
ternal 200
μ
A current source (I
OCSET
), and the
MOSFET’s on-resistance(R
DS(ON)
) set the converter’s
over-current (OC) trip point according to the follow-
ing equation:
I
PEAK
=
OUT
R
GND
R
T
I
OCSET
x
R
OCSET