参数资料
型号: APW7060K
厂商: Anpec Electronics Corporation
英文描述: Dual Controllers - Step Down Synchronous PWM and Linear Controller
中文描述: 双控制器-向下同步PWM和线性控制器步
文件页数: 12/16页
文件大小: 179K
代理商: APW7060K
Copyright
ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
APW 7060
www.anpec.com.tw
12
where Iout is the maximum load current
V
out2
is the nominal output voltage
In some applications, heatsink maybe required to help
maintain the junction temperature of the MOSFET be-
low its maximum rating.
Layout Considerations
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator.
In general, interconnecting impedances should be mini-
mized by using short, wide printed circuit traces. Sig-
nal and power grounds are to be kept separate and
finally combined using ground plane construction or
single point grounding. Figure 5 illustrates the layout,
with bold lines indicating high current paths. Compo-
nents along the bold lines should be placed close
together. Below is a checklist for your layout:
Keep the switching nodes (UGATE, LGATE and
the PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. There
fore keep traces to these nodes as short as
possible.
Decoupling capacitor C
IN
provides the bulk capaci
tance and needs to be placed close to the drain of
Q1.
Application I nformation
Figure 5. Recommended Layout Diagram
APW7060
UGATE
LGATE
5VCC
GND
PHASE
5VCC
GND
12VCC
V
IN
V
OUT
Q1
L1
C
OUT
C
IN
C
HF
12VCC
Q2
C
BP
C
BP
d
Time
V
DS
tsw
Figure 4. Switching waveform across MOSFET
The ground return of C
IN
must return to the combine
C
OUT
(-) terminal.
Capacitor C
HF
is to improve noise performance and
a small 1uF ceramic capacitor will be sufficient. Place
this capacitor close of the drain of Q1.
Inductor L1 should be connected closely to the
PHASE node.
Bypass capacitors, C
BP
, should be placed as close
to the 5VCC and 12VCC pins.
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