参数资料
型号: AS1106WL
厂商: ams
文件页数: 9/22页
文件大小: 0K
描述: IC LED 8-DIGIT DRIVER 24-SOIC
标准包装: 31
显示器类型: LED
配置: 7 段 + DP
接口: 串行
数字或字符: 8 位数字
电流 - 电源: 330mA
电源电压: 2.7 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC
包装: 管件
产品目录页面: 804 (CN2011-ZH PDF)
AS1106, AS1107
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
8.1 AS1106 vs. AS1107
The AS1106 and AS1107 are identical except for two features:
The AS1107 segment drivers are slew-rate limited to reduce electromagnetic interference (EMI).
The AS1107 serial interface is fully SPI compatible (programmable for AS1106).
8.2 Serial-Addressing Format
Programming the AS1106/AS1107 is done by writing to the device’s internal registers (see Digit- and Control-Registers on page 9) via the 4-wire
serial interface. A programming sequence consists of 16-bit packages as listed in Table 6 .
The data is shifted into the internal 16-bit register with the rising edge of the CLK signal. With the rising edge of the LOAD/CSN signal the data is
latched into a digit- or control-register. The LOAD/CSN signal must go high after the 16th rising clock edge.
The LOAD/CSN signal can also come later but this must happen just before the next rising edge of CLK, otherwise the data will be lost. The
contents of the internal shift register are applied 16.5 clock cycles later to pin DOUT. The data is clocked out at the falling edge of CLK.
The first 4 bits (D15:D12) are “don't care”, bits D11:D8 contain the register address, and bits D7:D0 contain the data. The first bit is D15, the most
significant bit (MSB). The exact timing is shown in Figure 12 .
Table 6. 16-Bit Serial Data Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
Register Address (see Table 7 )
MSB
Data
LSB
8.3 Initial Power-Up
On initial power-up, the AS1106/AS1107 registers are reset to their default values, the display is blanked, and the device goes into shutdown
mode. At this time, all registers should be programmed for normal operation.
Note: The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control Register (see page 12)
is set to the minimum values.
Figure 12. Interface Timing
LOAD/CSN
t CSW
t CSH
t CSS
t CL
t CH
t CP
t LDCK
CLK
t DS
t DH
DIN
D15
D14
D1
D0
t DO
DOUT
Revision 2.28
8 - 21
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