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AS1108
Datasheet - Electrical Characteristics
6 Electrical Characteristics
Conditions: V
DD
= 2.7 to 5.5V, R
SET
= 9.53k
Ω
±1%, T
AMB
= T
MIN
to T
MAX
(unless otherwise specified).
Table 3. Electrical Characteristics
Parameter
Symbol
Operating Supply Voltage
V
DD
Note:
All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or
SQC (Statistical Quality Control) methods.
Conditions
Min
2.7
Typ
5.0
Max
5.5
Unit
V
Shutdown Supply Current
I
DDSD
All digital inputs at V
DD
or GND,
T
AMB
= +25oC
R
SET
= open circuit.
All segments and decimal point
on; I
SEG
= -40mA.
4 digits scanned
V
OUT
= 0.65V
V
DD
= 5.0V, V
OUT
= (V
DD
-1V)
10
μA
Operating Supply Current
I
DD
1
mA
330
Display Scan Rate
Digit Drive Sink Current
Segment Drive Source Current
Segment Drive Current Matching
Digit Drive Source Current
Segment Drive Sink Current
Slow Segment Blink Period (ON
phase, Internal Oscillator)
Fast Segment Blink Period
(ON phase, Internal Oscillator)
Fast or Slow Segment Blink Duty
Cycle (Guaranteed by design)
f
OSC
I
DIGIT
I
SEG
Δ
I
SEG
I
DIGIT
I
SEG
1000
320
-30
1600
2600
Hz
mA
mA
%
mA
mA
-40
3.0
-45
Digit off, V
DIGIT
= (V
DD
- 0.3V)
Segment off, V
SEG
= 0.3V
-2
5
t
SLOWBLINK
0.64
1
1.65
s
t
FASTBLINK
0.32
0.5
0.83
s
49.9
50
50.1
%
Table 4. Logic Inputs/Outputs Characteristics
Parameter
Input Current DIN, CLK, LOAD/CSN
Logic High Input Voltage
Symbol
I
IH
, I
IL
V
IH
Conditions
V
IN
= 0V or V
DD
Min
-1
Typ
Max
1
Unit
μA
V
0.7 x V
DD
Logic Low Input Voltage
V
IL
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
DOUT, I
SOURCE
= -1mA,
V
DD
= 5.0V ± 10%
DOUT, I
SOURCE
= -1mA,
V
DD
= 3.0V ± 10%
DOUT, I
SINK
= 1.6mA
DIN, CLK, LOAD/CSN
0.8
0.6
V
Output High Voltage
V
OH
V
DD
- 1
V
V
DD
- 0.5
Output Low Voltage
Hysteresis Voltage
V
OL
Δ
V
I
0.4
V
V
1
Table 5. Timing Characteristics
(see Figure 10 on page 7)
Parameter
CLK Clock Period
CLK Pulse Width High
CLK Pulse Width Low
CSMFall-to-CLK Rise Setup Time
(AS1108 SPI-programmed)
CLK Rise-to -LOAD/CSN Rise Hold Time
DIN Setup Time
DIN Hold Time
Output Data Propagation Delay
LOAD Rising Edge-to-Next Clock Rising Edge
Minimum LOAD/CSN Pulse High
Data-to-Segment Delay
Symbol
t
CP
t
CH
t
CL
Conditions
Min
100
50
50
Typ
Max
Unit
ns
ns
ns
t
CSS
25
ns
t
CSH
t
DS
t
DH
t
DO
t
LDCK
t
CSW
t
DSPD
0
25
0
ns
ns
ns
ns
ns
ns
ms
C
LOAD
= 50pF
25
50
50
2.25