参数资料
型号: AS1116 DB-YELLOW
厂商: ams
文件页数: 10/24页
文件大小: 0K
描述: BOARD DEMO AS1116 YELLOW
标准包装: 1
电流 - 输出 / 通道: *
输出及类型: 8,非隔离
输出电压: *
特点: 64 LED 驱动器,带错误检测,SPI
输入电压: 2.7 ~ 5.5 V
已供物品:
已用 IC / 零件: AS1116
AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
Serial Interface
The AS1116 contains a 16bit SPI interface to access the internal data and control registers of the device (see Digit- and Control-Registers
on page 11) . The SPI interface is driven with the rising edge of SCL. A falling edge on LD signal indicates the beginning of an access on the
SPI interface, the rising edge on LD determines an access on SPI. An access must consist of exactly 16bits for write operation and 8bits for read
operation. Timing restrictions on the SPI interface pins are defined in Figure 19 .
Table 6 shows the structure of the 16bit command word for writing data. The bits D0 to D7 are the data information, bits D8 to D12 are the
address bits, D13 is set to ‘0’, bit D14 is defining the read (D14 = ‘1’) or the write (D14 = ‘0’) configuration and bit D15 is a don’t care bit.
In Table 7 on page 11 the 8bit command word for the read operation can be found.
Bit D0 (write operation) or bit D8 (read operation) is the first bit to shift into the SPI interface after the falling edge of LD. Bit D15 is the last bit to
write to SPI before rising edge of LD.
At a read operation an 8bit operation is executed (see Figure 18) . At the first rising edge of SCL after the rising edge of LD D7 of addressed
register is written to SDO pin. At the next rising edge of SCL D6 is written to SDO pin. LD must be kept high during reading data from a internal
data or control register of AS1116.
Table 6. 16-Bit Serial Data Format
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
LSB
Data
MSB
Register Address (see Table 7 )
0
R/W
X
Figure 17. Write operation
1
8
9
16
SCL
LD
SDI
SDO
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9 D10 D11 D12 D13 D14 D15
D9 D10 D11 D12 D13 D14 D15
Figure 18. Read operation
1
8
9
16
SCL
LD
SDI
D8
D9 D10 D11 D12 D13 D14 D15
SDO
D7
D6
D5
D4
D3
D2
D1
D0
Revision 1.08
9 - 23
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