参数资料
型号: AS3515
厂商: ams
文件页数: 15/67页
文件大小: 0K
描述: IC CODEC AFE AUDIO STER 64-CABGA
标准包装: 476
类型: 音频编解码器
应用: 便携式音频,电话
安装类型: 表面贴装
封装/外壳: 64-TFBGA
供应商设备封装: 64-CTBGA(7x7)
包装: 托盘
AS3515 V15
austriamicrosystems
Data Sheet, Confidential
www.austriamicrosystems.com
Revision 3.1
21
- 66
6.6
Digital Audio Interface
6.6.1
Input
Digital audio data can be fed into the AS3515 via the I2S interface These input data are then used by the 18-bit DAC to generate the
analog audio signal.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
40.5dB to +6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
6.6.2
Output
This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is then fed through a
volume control to the 14 bit ADC. The digital output is done via an I2S interface.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
34.5dB to +12dB. The stage is set to mute by default. If the ADC output is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling rate.
6.6.3
Signal Description
The digital audio interface uses the standard I2S format:
left justified
MSB first
one additional leading bit
The first 18 bits are taken for DAC conversion. The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than
18 bits sampled, the data sample is completed with “0”s. The ADC output is always 16 bit. If more SCLK pulses are provided, only the first
16 will be significant. All following bit will be “0”.
SCLK has not to be necessarily synchronous to LRCK but the high going edge has to be separate from LRCK edges. The LRCK signal
has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always
in correct phase lock condition to the external LRCK.
Figure 8 I2S_Timing
15
2
1
0
17
2
1
0
Left Channel
15
2
1
0
17
2
1
0
Right Channel
LRCK
SCLK
SDO
16 bit
SDI
18 bit
tsu thd
ts1 ts2
leading dummy bit
according to I2S
standard
*
6.6.4
Power Save Options
The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption.
6.6.5
Clock Supervision
The digital audio interface automatically checks the LRCK. An interrupt can be generated when the state of the LRCK input changes. A bit
in the interrupt register represents the actual state (present or not present) of the LRCK.
ams
AG
Technical
content
still
valid
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