参数资料
型号: AS3658C-BCTP
厂商: ams
文件页数: 92/158页
文件大小: 0K
描述: IC PMU POWER/AUDIO 124-CTBGA
标准包装: 2,500
应用: 便携式设备
电流 - 电源: 7mA
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 124-TFBGA
供应商设备封装: 124-CTBGA(8x8)
包装: 带卷 (TR)
AS3658
Data Sheet Confidential
- Detailed Description- Audio Functions
Table 90. AudioSet2Register
Addr:75
Audio Set2
These bits control the Audio functions
Bit
Bit Name
Default Access
Description
Bias current reduction settings for headphone output
00
0%
5,4
ibr_hph<1:0>
0
R/W
01
17%
10
11
34%
50%
6
7
I2S_select
I2S_mclk_en
0
0
R/W
R/W
0
1
0
1
Select I2S_1 input
Select I2S_2 input
Generation of the master clock by the internal PLL
Use Pin MCLK_1, MCLK_2 as masterclock input
9.4
ADC, DAC and Digital Audio Input
9.4.1 General
Digital audio data can be fed into the AS3658 via the I2S interface This input data is used by the 18-bit DAC to
generate the analog audio signal.
The stage is set to mute by default; If the DAC input is not enabled.
9.4.2 Signal Description
The digital audio interface uses the standard I2S format:
Left justified
MSB first
One additional leading bit
MCLK has to have a fixed ratio of 128 or 256 to LRCLK. With a LRCLK equal to 16, 32, 44.1 or 48kHz, the MCLK can
be generated by the on-chip PLL (do not use the internal PLL if there is jitter on the LRCLK1 or 2). For lower sample
rates the bit pll_mode has to be set (for sample rates between 8kHz and 12kHz).
The high going edge of MCLK has to have timing separation from LRCLK edges. If the clock generation is so that
LRCLK edges are at the same time as MCLK high going edges, the MCLK can be inverted to guarantee a proper DAC
function.
This audio input interfaces uses an I2S synchronizer to be able to handle audio sample length of 24bits or less.
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