参数资料
型号: AS5134-ZSST
厂商: ams
文件页数: 7/33页
文件大小: 0K
描述: IC ENCODER PROG 20-SSOP
应用说明: AS5000 Series Magnet Selection Guide
AS5000 Series Magnets for Extended Vertical Range
产品培训模块: AS5134 Overview
特色产品: AS5134 High-Speed Magnetic Rotary Encoder
标准包装: 1
传感范围: 20mT ~ 80mT
类型: 线性,旋转编码器 - 可编程
电源电压: 4.5 V ~ 5.5 V
电流 - 电源: 22mA
输出类型: 数字,PWM
特点: 可编程
工作温度: -40°C ~ 140°C
封装/外壳: 20-SSOP(0.209",5.30mm 宽)
供应商设备封装: 20-SSOP
包装: 标准包装
产品目录页面: 804 (CN2011-ZH PDF)
其它名称: AS5134-ZSSTDKR
AS5134
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS Outputs: DIO, PWM, DX
V OH
V OL
CL
High level output voltage
Low level output voltage
Capacitive load
Source current < 4mA
Sink current < 4mA
V DD -0.5
0
V DD
V SS +0.4
35
V
V
pF
CMOS Tristate Output: DIO
IO Z
Tristate leakage current
CS = low
1
μA
6.1 Timing Characteristics
Table 4. Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
2-/3-Wire Data Transmission
3-Wire Interface
f DCLK
f DCLK,P
Clock Frequency
Clock Frequency
Normal operation
During OTP programming
200
5
6
650
MHz
kHz
2-Wire Interface
f DCLK
f DCLK,P
Clock Frequency
Clock Frequency
Normal operation
During OTP programming
0.1
200
5
6
500
MHz
kHz
General Data Transmission
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t TO
t CLK
Rising DCLK to CS
Chip select to positive edge of DCLK
Chip select to drive bus externally
Setup time command bit,
Data valid to positive edge of DCLK
Hold time command bit,
Data valid after positive edge of DCLK
Float time,
Positive edge of DCLK for last command
bit to bus float
Bus driving time,
Positive edge of DCLK for last command
bit to bus drive
Setup time data bit,
Data valid to positive edge of DCLK
Hold time data bit,
Data valid after positive edge of DCLK
Hold time chip select,
Positive edge DCLK to negative edge of
chip select
Bus floating time,
Negative edge of chip select to float bus
Timeout period in 2-wire mode (from
rising edge of DCLK)
Clock Timing
15
15
-
30
30
30
DCLK/2
+0
DCLK/2
+0
DCLK/2
+0
30
0
17
200
-
-
-
-
DCLK/2
DCLK/2
+30
DCLK/2
+30
DCLK/2
+30
30
27
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
www.austriamicrosystems.com/AS5134
Revision 2.3
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