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| 型号： | AS5215OM-HMFP-500 |
| 厂商： | ams |
| 文件页数： | 16/27页 |
| 文件大小： | 0K |
| 描述： | IC ENCODER ROTARY 32-QFN |
| 应用说明： | AS5000 Series Magnet Selection Guide AS5000 Series Magnets for Extended Vertical Range |
| 特色产品： | AS5215 - Automotive Rotary Encoder IC |
| 标准包装： | 1 |
| 传感范围： | 20mT ~ 80mT |
| 类型： | 线性，旋转编码器 - 可编程 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 28mA |
| 输出类型： | 模拟 |
| 特点： | 可编程 |
| 工作温度： | -40°C ~ 150°C |
| 封装/外壳： | 32-VQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（7x7） |
| 包装： | 标准包装 |
| 其它名称： | AS5215-HQFT-500DKR AS5215-HQFT-500DKR-ND AS5215-HQFT-OM-500DKR AS5215-HQFT-OM-500DKR-ND AS5215OM-HMFP-500DKR |
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AS5215
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8 Application Information
8.1 Sleep Mode
The target is to provide the possibility to reduce the total current consumption. No output signal will be provided when the IC is in sleep mode.
Enabling or disabling sleep mode is done by sending the SLEEP or WAKEUP commands via. the SSI interface. Analog blocks are powered
down with respect to fast wake up time.
8.2 SSI Interface
The setup for the device is handled by the digital interface. Each communication starts with the rising edge of the chip select signal. The
synchronization between the internal free running analog clock oscillator and the external used digital clock source for the digital interface is
done in a way that the digital clock frequency can vary in a wide range.
Table 8. SSI Interface Pin Description
Port
Chip select
DCLK
Bidirectional data input output
Symbol
CS
DCLK
DIO
Function
Indicates the start of a new access cycle to the device
CS = LO → reset of the digital interface
Clock source for the communication over the digital interface
Command and data information over one single line
The first bit of the command defines a read or write access
Table 9. SSI Interface Parameter Description
Symbol
f_DCLK
f_EZ_RW
f_EZ_PR
OG
f_EZ_AR
B
Parameter
Clock frequency at normal operation
Clock frequency at easy zap read
write access
Clock frequency at easy zap access
program OTP
Clock frequency at easy zap analog
readback
Notes
The nominal value for the clock frequency can
be derived from a 10MHz oscillator source.
Correct access to the programmable zener
diode block needs a strict timing – the zap pulse
is exact one period.
The nominal value for the clock frequency can
be derived from a 10MHz oscillator source.
20pF external load allowed.
The nominal value for the clock frequency can
be derived from a 10MHz oscillator source.
Min
no limit
no limit
200
no limit
Typ
5
5
-
156.3
Max
6
6
650
162.5
Unit
MHz
kHz
kHz
kHz
Interface General at normal mode
Protocol: 5 command bit + 16 data input output
Command
Data
Interface General at extended mode
Protocol: 5 command bit + 46 data input output
Command
Data
Interface Modes
Normal read operation mode
Extended read operation mode
Normal write operation mode
Extended write operation mode
5 bit command: cmd<4:0> ← bit<21:16>
16 bit data: data<15:0> ← bit<15:0>
5 bit command: cmd<4:0> ← bit<50:46>
34 bit data: data<45:0> ← bit<45:0>
cmd<4:0> = <00xxx> → 1 DCLK per data bit
cmd<4:0> = <01xxx> → 4 DCLK per data bit
cmd<4:0> = <10xxx> → 1 DCLK per data bit
cmd<4:0> = <11xxx> → 4 DCLK per data bit
www.austriamicrosystems.com/AS5215
Revision 1.11
15 - 26
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