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| 型号： | AS7C31025B-15TJIN |
| 厂商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分类： | DRAM |
| 英文描述： | 3.3V 128K X 8 CMOS SRAM (Center power and ground) |
| 中文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封装： | 0.300 INCH, LEAD FREE, SOJ-32 |
| 文件页数： | 2/9页 |
| 文件大小： | 99K |
| 代理商： | AS7C31025B-15TJIN |
AS7C31025B
3/24/04, v. 1.3
Alliance Semiconductor
P. 2 of 9
Functional description
The AS7C31025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x 8
bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5, 6, 7, 8 ns are ideal for
high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When
CE
is high the device enters standby mode. A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CE
). Data
on the input pins I/O0 through I/O7 is written on the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with
output enable (
OE
) or write enable
(
WE
).
A read cycle is accomplished by asserting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025B is packaged in common
industry standard packages.
Absolute maximum ratings
NOTE: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = don’t care, L = low, H = high.
Parameter
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–
–65
–55
–
Max
+5.0
Unit
V
V
W
o
C
o
C
mA
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
V
CC
+ 0.5
1.0
+150
+125
20
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
D
OUT
D
IN
Mode
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (I
CC
)
相关PDF资料 |
PDF描述 |
|---|---|
| AS7C31025B-20TJIN | 3.3V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C31025B | 3.3V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C31025B-12TJI | 8-Bit Parallel-Load Shift Registers 16-SOIC -40 to 85 |
| AS7C31025B-15JC | 8-Bit Parallel-Load Shift Registers 16-SSOP -40 to 85 |
| AS7C31025B-15JCN | 8-Bit Parallel-Load Shift Registers 16-SSOP -40 to 85 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AS7C31025B-20JC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C31025B-20JCN | 功能描述:静态随机存取存储器 1M, 3.3V, 20ns, FAST 128K x 8 Asynch 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| AS7C31025B-20JCNTR | 功能描述:静态随机存取存储器 1M, 3.3V, 20ns, FAST 128K x 8 Asynch 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| AS7C31025B-20JI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C31025B-20JIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 8 CMOS SRAM (Center power and ground) |
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