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参数资料
| 型号： | AS7C33128NTD32B-133TQIN |
| 厂商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分类： | DRAM |
| 英文描述： | 3.3V 128Kx32/36 Pipelined SRAM with NTD |
| 中文描述： | 128K X 32 ZBT SRAM, 4 ns, PQFP100 |
| 封装： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件页数： | 5/18页 |
| 文件大小： | 435K |
| 代理商： | AS7C33128NTD32B-133TQIN |
AS7C33128NTD32B
AS7C33128NTD36B
2/8/05; v.1.5
Alliance Semiconductor
P. 5 of 18
S
ignal descriptions
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of SNOOZE
MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs except ZZ is
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
Burst order
Signal
CLK
CEN
A, A0, A1
DQ[a,b,c,d]
CE0, CE1,
CE2
I/O
Properties
CLOCK
SYNC
SYNC
SYNC
Description
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is high.
Advance or Load. When sampled high, the internal burst address counter will increment in the
order defined by the LBO input value. When low, a new address is loaded.
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
I
I
I
I/O
I
SYNC
ADV/LD
I
SYNC
R/W
I
SYNC
BW[a,b,c,d]
I
SYNC
OE
I
ASYNC
LBO
I
STATIC
Selects Burst mode. When tied to V
DD
or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order.
This signal is internally pulled High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connect
ZZ
NC
I
-
ASYNC
-
Interleaved burst order (LBO = 1)
A1 A0
Starting address
0 0
First increment
0 1
Second increment
1 0
Third increment
1 1
Linear burst order (LBO = 0)
A1 A0
Starting Address
First increment
Second increment
Third increment
A1 A0
0 1
0 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
1 0
0 1
0 0
A1 A0
0 1
1 0
1 1
0 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
0 0
0 1
1 0
0 0
0 1
1 0
1 1
相关PDF资料 |
PDF描述 |
|---|---|
| AS7C33128NTD32B-166TQC | 3.3V 128Kx32/36 Pipelined SRAM with NTD |
| AS7C33128NTD32B-166TQCN | 3.3V 128Kx32/36 Pipelined SRAM with NTD |
| AS7C33128NTD32B-166TQI | 3.3V 128Kx32/36 Pipelined SRAM with NTD |
| AS7C33128NTD32B-166TQIN | 3.3V 128Kx32/36 Pipelined SRAM with NTD |
| AS7C33128NTD32B-200TQC | 3.3V 128Kx32/36 Pipelined SRAM with NTD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AS7C33128NTD32B-166TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128Kx32/36 Pipelined SRAM with NTD |
| AS7C33128NTD32B-166TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128Kx32/36 Pipelined SRAM with NTD |
| AS7C33128NTD32B-166TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128Kx32/36 Pipelined SRAM with NTD |
| AS7C33128NTD32B-166TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128Kx32/36 Pipelined SRAM with NTD |
| AS7C33128NTD32B-200TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128Kx32/36 Pipelined SRAM with NTD |
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