参数资料
型号: AS7C33128NTD32B
厂商: Alliance Semiconductor Corporation
英文描述: 3.3V 128Kx32/36 Pipelined SRAM with NTD
中文描述: 3.3 128Kx32/36流水线与新台币的SRAM
文件页数: 15/18页
文件大小: 435K
代理商: AS7C33128NTD32B
AS7C33128NTD32B
AS7C33128NTD36B
2/8/05; v.1.5
Alliance Semiconductor
P. 15 of 18
AC test conditions
Output Load: see Figure B,
except for
t
LZC
, t
LZOE
, t
HZOE
, t
HZC
see Figure C.
Input pulse level: VSS to 3V. See Figure A.
Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Notes
Z
0
=50
D
out
50
V
L
=1.5V
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
VSS
90%
10%
+3.0V
353
/ 1538
5 pF*
319
/ 1667
D
OUT
GND
Figure C: Output load (B)
*including scope
and jig capacitance
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
1
2
3
4
For test conditions, see
AC Test Conditions
, Figures A, B, C.
This parameter measured with output load condition in Figure C
This parameter is sampled and not 100% tested.
t
HZOE
is less than t
LZOE
; and t
HZC
is less than t
LZC
at any given temper-
ature and voltage.
t
HZCN
is a
‘no load’ parameter to indicate exactly when SRAM outputs
have stopped driving.
5
6
t
CH
measured as HIGH above VIH, and t
CL
measured as LOW below
VIL
This is a synchronous device. All addresses must meet the specified
setup and hold times for all rising edges of CLK. All other synchronous
inputs must meet the setup and hold times with stable logic levels for all
rising edges of CLK when chip is enabled.
7
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