参数资料
型号: AS7C33128NTF32B-10TQCN
厂商: ALLIANCE SEMICONDUCTOR CORP
元件分类: DRAM
英文描述: LM392 Low Power Operational Amplifier/Voltage Comparator; Package: SOIC NARROW; No of Pins: 8; Qty per Container: 95; Container: Rail
中文描述: 128K X 32 ZBT SRAM, 10 ns, PQFP100
封装: 14 X 20 MM, LEAD FREE, TQFP-100
文件页数: 6/18页
文件大小: 416K
代理商: AS7C33128NTF32B-10TQCN
AS7C33128NTF32B/36B
4/13/05, v 1.3
Alliance Semiconductor
P. 6 of 18
Synchronous truth table
[5,6,7,8,9,11]
Key
: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or more byte write signals are
LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial BEGIN BURST
cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given,
but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. OE may be used
when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No
WRITE operations will be performed during the INHIBIT CLOCK cycle.
5 BWa enables WRITEs to byte “a” (DQa pins); BWb enables WRITEs to byte “b” (DQb pins); BWc enables WRITEs to byte “c” (DQc pins); BWd enables WRITEs to byte “d”
(DQd pins).
6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting CEN HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low.
CE0
CE1
CE2 ADV/LD R/W
BWn
OE
CEN
Address
source
NA
NA
NA
NA
External L to H
Next
External L to H NOP/DUMMY READ (Begin Burst)
Next
L to H
DUMMY READ (Continue Burst)
External L to H
WRITE CYCLE (Begin Burst)
Next
L to H
WRITE CYCLE (Continue Burst)
External L to H
NOP/WRITE ABORT (Begin Burst) High-Z
CLK
Operation
DQ
Notes
H
X
X
X
L
X
L
X
L
X
L
X
X
L
X
H
X
H
X
H
X
H
X
H
X
X
L
X
L
X
L
X
L
L
L
L
H
L
H
L
H
L
H
L
X
X
X
X
H
X
H
X
L
X
L
X
X
X
X
X
X
X
X
L
L
H
X
X
X
X
L
L
H
H
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L to H
L to H
L to H
L to H
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
CONTINUE DESELECT Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
High-Z
High-Z
High-Z
High-Z
Q
Q
High-Z
High-Z 1,2,10
D
D
1
L to H
1,10
2
3
1,3,10
2,3
1,2,3,
10
4
X
X
X
H
X
H
X
L
Next
L to H
WRITE ABORT (Continue Burst)
High-Z
X
X
X
X
X
X
X
H
Current L to H
INHIBIT CLOCK
-
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相关代理商/技术参数
参数描述
AS7C33128NTF32B-10TQI 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K x 32/36 Flowthrough Synchronous SRAM with NTD
AS7C33128NTF32B-10TQIN 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K x 32/36 Flowthrough Synchronous SRAM with NTD
AS7C33128NTF32B-75TQC 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K x 32/36 Flowthrough Synchronous SRAM with NTD
AS7C33128NTF32B-75TQCN 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K x 32/36 Flowthrough Synchronous SRAM with NTD
AS7C33128NTF32B-75TQI 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K x 32/36 Flowthrough Synchronous SRAM with NTD