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参数资料
| 型号： | AS7C33128PFD32B-166TQC |
| 厂商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分类： | DRAM |
| 英文描述： | 3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| 中文描述： | 128K X 32 STANDARD SRAM, 3.5 ns, PQFP100 |
| 封装： | 14 X 20 MM, TQFP-100 |
| 文件页数： | 5/19页 |
| 文件大小： | 552K |
| 代理商： | AS7C33128PFD32B-166TQC |
AS7C33128PFD32B
AS7C33128PFD36B
1/31/05; v.1.1
Alliance Semiconductor
P. 5 of 19
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs except ZZ is
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
Signal descriptions
Signal
I/O
Properties
Description
CLK
A,A0,A1
I
I
CLOCK
SYNC
Clock. All inputs except
OE
, ZZ,
LBO
are synchronous to this clock.
Address. Sampled when all chip enables are active and
ADSC
or
ADSP
are asserted.
DQ[a,b,c,d]
I/O
SYNC
Data. Driven as output when the chip is enabled and
OE
is active.
CE0
I
SYNC
Master chip enable. Sampled on clock edges when
ADSP
or
ADSC
is active. When
CE0
is inactive,
ADSP
is blocked. Refer to the Synchronous Truth Table for more information.
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when
ADSC
is active or when
CE0
and
ADSP
are active.
CE1,
CE2
I
SYNC
ADSP
I
SYNC
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
ADSC
ADV
I
I
SYNC
SYNC
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
Advance. Asserted LOW to continue burst read/write.
GWE
I
SYNC
Global write enable. Asserted LOW to write all 32/36 bits. When High,
BWE
and
BW[a:d]
control write enable.
BWE
I
SYNC
Byte write enable. Asserted LOW with
GWE
= HIGH to enable effect of
BW[a:d]
inputs.
Write enables. Used to control write of individual bytes when
GWE
= HIGH and
BWE
=
Low. If any of
BW[a:d]
is active with
GWE
= HIGH and
BWE
= LOW the cycle is a
write cycle. If all
BW[a:d]
are inactive the cycle is a read cycle.
BW[a,b,c,d]
I
SYNC
OE
I
ASYNC
Asynchronous output enable. I/O pins are driven when
OE
is active and the chip is in read
mode.
LBO
I
STATIC
Selects Burst mode. When tied to V
DD
or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order.
This signal is internally
pulled High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
ZZ
I
ASYNC
NC
-
-
No connect
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| AS7C33128PFD32B-166TQCN | 3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-166TQI | 3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-166TQIN | 3.3V 128K X 32/36 pipeline burst synchronous SRAM |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AS7C33128PFD32B-166TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-166TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-166TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-200TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-200TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 32/36 pipeline burst synchronous SRAM |
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