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参数资料
| 型号： | AS7C33128PFD32B-166TQCN |
| 厂商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分类： | DRAM |
| 英文描述： | 3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| 中文描述： | 128K X 32 STANDARD SRAM, 3.5 ns, PQFP100 |
| 封装： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件页数： | 4/19页 |
| 文件大小： | 552K |
| 代理商： | AS7C33128PFD32B-166TQCN |
AS7C33128PFD32B
AS7C33128PFD36B
1/31/05; v.1.1
Alliance Semiconductor
P. 4 of 19
Functional description
The AS7C33128PFD32B and AS7C33128PFD36B are high-performance CMOS 4-Mbit synchronous Static Random Access
Memory (SRAM) devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline
for highest frequency on any given technology.
Timing for these devices is compatible with existing Pentium
synchronous cache specifications. This architecture is suited
for ASIC, DSP and PowerPC
1
-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 5.0/6.0/7.5 ns with clock access times (t
CD
) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus
frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the
controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent
internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In
a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when ADV is sampled Low, and both address strobes are High. Burst mode is selectable with the
LBO
input. With
LBO
unconnected or driven High, burst operations use a Pentium
count sequence. With
LBO
driven LOW, the
device uses a linear count sequence suitable for PowerPC
and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more
bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled
Low. Address is incremented internally to the next burst address if BWn and ADV are sampled Low. This device operates in
double-cycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP are as follows:
ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
Master chip enable CE0 blocks ADSP, but not ADSC.
AS7C33128PFD32B and AS7C33128PFD36B family operates from a core 3.3V power supply. I/Os use a separate power
supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package
TQFP capacitance
* Guaranteed not tested
TQFP thermal resistance
1 PowerPC
is a trademark International Business Machines Corporation.
Parameter
Symbol
Test conditions
Min
Max
Unit
Input capacitance
C
IN*
C
I/O*
V
IN
= 0V
-
5
pF
I/O capacitance
V
OUT
= 0V
-
7
pF
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(junction to ambient)
1
1 This parameter is sampled
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
1–layer
θ
JA
θ
JA
40
°
C/W
4–layer
22
°
C/W
Thermal resistance
(junction to top of case)
1
θ
JC
8
°
C/W
相关PDF资料 |
PDF描述 |
|---|---|
| AS7C33128PFD32B-166TQI | 3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-166TQIN | 3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-200TQC | 3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-200TQCN | 3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-200TQI | 3.3V 128K X 32/36 pipeline burst synchronous SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AS7C33128PFD32B-166TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-166TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-200TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-200TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 32/36 pipeline burst synchronous SRAM |
| AS7C33128PFD32B-200TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 32/36 pipeline burst synchronous SRAM |
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