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参数资料
| 型号： | AS8F128K32Q-150/XT |
| 厂商： | AUSTIN SEMICONDUCTOR INC |
| 元件分类： | PROM |
| 英文描述： | 128K x 32 FLASH FLASH MEMORY ARRAY |
| 中文描述： | 128K X 32 FLASH 5V PROM MODULE, 150 ns, CQFP68 |
| 封装： | CERAMIC, QFP-68 |
| 文件页数： | 19/22页 |
| 文件大小： | 1260K |
| 代理商： | AS8F128K32Q-150/XT |
FLASH
AS8F128K32
AS8F128K32
Rev. 2.7 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
Austin Semiconductor, Inc.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device to
reading array data.
All addresses are latched on the falling edge of WEx\ or
CEx\, whichever happens later. All data is latched on the rising
edge of WEx\ or CEx\, whichever happens first. Refer to the
appropriate timing diagrams in the “AC Characteristics”
section.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
The system must issue the reset command to re-enable the
device for reading array data if I/O5* goes high, or while in the
autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information. The
Read Operations table provides the read parameters, and Read
Operation Timings diagram shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device
to reading array data. Address bits are don’t care for this
command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing begins.
This resets the device to reading array data. Once erasure
begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data. Once
programming begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to return
to reading array data.
If I/O5* goes high during a program or erase operation,
writing the reset command returns the device to reading array
data.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes, and
determine whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by writing
two unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h or retrieves the
manufacturer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address (SA) and
the address 02h in returns 01h if that sector is protected, or 00h
if it is unprotected. Refer to the Sector Address tables for valid
sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The program
address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to
provide further controls or timings. The device automatically
provides internally generated program pulses and verify the
programmed cell margin. The Command Definitions take shows
the address and data requirements for the byte program
command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are no
longer latched. The system can determine the status of the
program operation by using I/O7or I/O6. See “Write Operation
Status” for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a “0”
back to a “1”. Attempting to do so may halt the operation and
set I/O5* to “1”, or cause the Data\ Polling algorithm to indicate
the operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
*NOTE: applies to every 8th byte (i.e. I/O5, I/O13, I/O21, I/O29)
相关PDF资料 |
PDF描述 |
|---|---|
| AS8F128K32Q1-60/883C | 128K x 32 FLASH FLASH MEMORY ARRAY |
| AS8F128K32Q1-60/IT | 128K x 32 FLASH FLASH MEMORY ARRAY |
| AS8F128K32Q1-60/Q | 128K x 32 FLASH FLASH MEMORY ARRAY |
| AS8F128K32Q1-60/XT | 128K x 32 FLASH FLASH MEMORY ARRAY |
| AS8F128K32Q1-70/883C | 128K x 32 FLASH FLASH MEMORY ARRAY |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AS8F128K32Q1-60/883C | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:128K x 32 FLASH FLASH MEMORY ARRAY |
| AS8F128K32Q1-60/IT | 制造商:Micross Components 功能描述:FLASH-MCM,4 MB - Trays |
| AS8F128K32Q1-60/Q | 制造商:Micross Components 功能描述:FLASH-MCM,4 MB - Trays |
| AS8F128K32Q1-60/XT | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:128K x 32 FLASH FLASH MEMORY ARRAY |
| AS8F128K32Q1-70/883C | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:128K x 32 FLASH FLASH MEMORY ARRAY |
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