参数资料
型号: ASM3P2762AG-06OR
厂商: ON SEMICONDUCTOR
元件分类: 时钟产生/分配
英文描述: 13 MHz, OTHER CLOCK GENERATOR, PDSO6
封装: GREEN, TSOT-23, 6 PIN
文件页数: 1/12页
文件大小: 361K
代理商: ASM3P2762AG-06OR
ASM3P2762A
Low Power Peak EMI
Reducing Solution
2010 SCILLC. All rights reserved.
Publication Order Number:
JANUARY 2010 – Rev. 2
ASM3P2762/D
Features
Generates an EMI optimized clock signal at the
output.
Integrated loop filter components.
Operates with a 3.3V / 2.5V Supply.
Operating current less than 6mA.
Low power CMOS design.
Input frequency range: 6MHz to 12MHz for 2.5V
6MHz to 13MHz for 3.3V
Generates a 1X low EMI spread spectrum clock of
the input frequency.
Frequency deviation: -1.25% (Typ) @ 10MHz Input
Frequency.
Available in 6-pin TSOT-23, 8-pin SOIC and 8-pin
TSSOP packages.
Product Description
The ASM3P2762A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. The ASM3P2762A reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. The ASM3P2762A allows significant
system cost savings by reducing the number of circuit
board layers, ferrite beads and shielding that are
traditionally required to pass EMI regulations.
The ASM3P2762A uses the most efficient and optimized
modulation
profile
approved
by
the
FCC
and
is
implemented by using a proprietary all digital method.
The ASM3P2762A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signals bandwidth is called spread
spectrum clock generation.
Applications
The ASM3P2762A is targeted towards all portable
devices with very low power requirements like MP3
players and digital still cameras.
Key Specifications
Description
Specification
Supply voltages
VDD = 3.3V /2.5V
Cycle-to-Cycle Jitter
200pS (Max)
Output Duty Cycle
45/55%
Modulation Rate Equation
FIN/256
Frequency Deviation
-1.25% (Typ) @ 10MHz
Block Diagram
VSS
XIN
ModOUT
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
PLL
VDD
PD
Crystal
Oscillator
XOUT
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