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| 型号： | AT17LV65A-10JI |
| 厂商： | Atmel |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC SRL CONFIG EEPROM 64K 20-PLCC |
| 标准包装： | 50 |
| 可编程类型： | 串行 EEPROM |
| 存储容量： | 64kb |
| 电源电压： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-LCC（J 形引线） |
| 供应商设备封装： | 20-PLCC |
| 包装： | 管件 |
5
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
4.1
DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
4.2
DCLK
Clock output or clock input. Rising edges on DCLK increment the internal address counter and
present the next bit of data to the DATA pin. The counter is incremented only if the RESET/OE
input is held High, the nCS input is held Low, and all configuration data has not been transferred
to the target device (otherwise, as the master device, the DCLK pin drives Low).
4.3
WP1
WRITE PROTECT (1). This pin is used to protect portions of memory during programming, and
it is disabled by default due to internal pull-down resistor. This input pin is not used during FPGA
loading operations. This pin is only available on AT17LV512A/010A/002A devices.
4.4
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low logic level
resets the address counter. A High logic level (with nCS Low) enables DATA and permits the
address counter to count. In the mode, if this pin is Low (reset), the internal oscillator becomes
inactive and DCLK drives Low. The logic polarity of this input is programmable and must be pro-
grammed active High (RESET active Low) by the user during programming for Altera
applications.
4.5
WP
Write protect (WP) input (when nCS is Low) during programming only (SER_EN Low). When
WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of
the memory cannot be written. This pin is only available on AT17LV65A/128A/256A devices.
4.6
nCS
Chip Select input (active Low). A Low input (with OE High) allows DCLK to increment the
address counter and enables DATA to drive out. If the AT17A series is reset with nCS Low, the
device initializes as the first (and master) device in a daisy-chain. If the AT17A series is reset
with nCS High, the device initializes as a subsequent AT17A series device in the chain.
4.7
GND
Ground pin. A 0.2 F decoupling capacitor between V
CC and GND is recommended.
4.8
nCASC
Cascade Select Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC pin of one
device is usually connected to the nCS input pin of the next device in the chain, which permits
DCLK from the master configurator to clock data from a subsequent AT17A series device in the
chain. This feature is not available on the AT17LV65A device.
4.9
A2
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AT17LV65A-10NC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10NI | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10PC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10PI | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10SC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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