参数资料
型号: AT17N002-10TQC
厂商: Atmel
文件页数: 17/18页
文件大小: 0K
描述: IC FPGA 2M CONFIG MEM 44TQFP
标准包装: 160
可编程类型: 串行 EEPROM
存储容量: 2Mb
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 44-TQFP
供应商设备封装: 44-TQFP(10x10)
包装: 托盘
配用: ATDH2225-ND - CABLE ISP FOR AT17
ATDH2200E-ND - CONFIGURATOR PROGRAM BOARD KIT
8
AT17N256/512/010/002/040
3020C–CNFG–08/07
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
DC Characteristics
V
CC = 3.3V ± 10%
Symbol
Description
AT17N256
AT17N512/
AT17N010
AT17N002/
AT17N040
Units
Min
Max
Min
Max
Min
Max
VIH
High-level Input Voltage
2.0
VCC
2.0
VCC
2.0
VCC
V
IL
Low-level Input Voltage
0
0.8
0
0.8
0
0.8
V
VOH
High-level Output Voltage
(IOH = -2.5 mA)
Commercial
2.4
V
VOL
Low-level Output Voltage
(IOL = +3 mA)
0.4
V
OH
High-level Output Voltage
(I
OH = -2 mA)
Industrial
2.4
V
VOL
Low-level Output Voltage
(IOL = +3 mA)
0.4
V
I
CCA
Supply Current, Active Mode
5
mA
IL
Input or Output Leakage Current
(VIN = VCC or GND)
-10
10
-10
10
-10
10
A
ICCS
Supply Current, Standby Mode
Commercial
50
100
150
A
Industrial
100
150
A
AC Characteristics
V
CC = 3.3V ± 10%
Symbol
Description
AT17N256
AT17N512/010/002/040
Units
Commercial
Industrial
Commercial
Industrial
Min
Max
Min
Max
Min
Max
Min
Max
TOE
OE to Data Delay
50
55
50
55
ns
T
CE to Data Delay
60
55
60
ns
T
CAC
CLK to Data Delay
75
80
55
60
ns
TOH
Data Hold from CE, OE, or CLK
0
ns
T
DF
CE or OE to Data Float Delay
55
50
ns
T
LC
CLK Low Time
25
ns
THC
CLK High Time
25
ns
T
SCE
CE Setup Time to CLK
(to guarantee proper counting)
35
60
30
35
ns
THCE
CE Hold Time from CLK
(to guarantee proper counting)
00
ns
THOE
OE High Time (guarantees counter is reset)
25
ns
FMAX
Maximum Clock Frequency
10
15
10
MHz
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