参数资料
型号: AT25160B-MAHL-T
厂商: Atmel
文件页数: 7/26页
文件大小: 0K
描述: IC EEPROM 16KBIT 20MHZ 8UDFN
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 16K (2K x 8)
速度: 5MHz,10MHz,20MHz
接口: SPI 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-UDFN
供应商设备封装: 8-UDFN(2x3)
包装: 标准包装
其它名称: AT25160B-MAHL-TDKR
AT25080B/160B
4.
Functional Description
The AT25080B/160B is designed to interface directly with the synchronous serial peripheral interface (SPI) of the
6805 and 68HC11 series of microcontrollers.
The AT25080B/160B utilizes an 8-bit instruction register. The list of instructions and their operation codes are con-
tained in Table 3-1 . All instructions, addresses, and data are transferred with the MSB first and start with a high-to-
low CS transition.
Table 4-1.
Instruction Set for the AT25080B/160B
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All program-
ming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly,
the Block Write Protection Bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 4-2.
Status Register Format
Bit 7
WPEN
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Table 4-3.
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Read Status Register Bit Definition
Definition
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle is in progress
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the device is write enabled
See Table 3-4 on page 8
See Table 3-4 on page 8
Bits 4–6 are “0”s when device is not in an internal write cycle
Bit 7 (WPEN)
See Table 3-5 on page 8
Bits 0–7 are “1”s during an internal write cycle
7
5228E–SEEPR–3/12
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