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参数资料
| 型号： | AT25320W-10SI |
| 厂商： | Atmel |
| 文件页数： | 8/21页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 32KBIT 3MHZ 8SOIC |
| 标准包装： | 94 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 32K (4K x 8) |
| 速度： | 3MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
Functional
Description
The AT25080/160/320/640 is designed to interface directly with the synchronous serial periph-
eral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25080/160/320/640 utilizes an 8-bit instruction register. The list of instructions and their
operation codes are contained in Table 1. All instructions, addresses, and data are transferred
with the MSB first and start with a high-to-low CS transition.
Table 1. Instruction Set for the AT25080/160/320/640
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power-up in the write disable state when V CC is
applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the sta-
tus of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be deter-
mined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of
protection employed. These bits are set by using the WRSR instruction.
Table 2. Status Register Format
Bit 7
WPEN
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Table 3. Read Status Register Bit Definition
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Definition
Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is
in progress.
Bit 1= 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the
device is WRITE ENABLED.
See Table 4 on page 9.
See Table 4 on page 9.
Bits 4 - 6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 5 on page 9.
Bits 0 - 7 are 1s during an internal write cycle.
8
AT25080/160/320/640
0675M–SEEPR–9/03
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