参数资料
型号: AT25F2048N-10SU-2.7
厂商: Atmel
文件页数: 9/19页
文件大小: 0K
描述: IC FLASH 2MBIT 33MHZ 8SOIC
标准包装: 100
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 2M (256K x 8)
速度: 33MHz
接口: SPI 3 线串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
其它名称: AT25F2048N10SU2.7
AT25F2048
The WRSR instruction also allows the user to enable or disable the Write Protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hard-
ware write protected, writes to the status register, including the block protect bits and the
WPEN bit, and the locked-out sectors in the memory array are disabled. Write is only
allowed to sectors of the memory which are not locked out. The WRSR instruction is
self-timed to automatically erase and program BP0, BP1, and WPEN bits. In order to
write the status register, the device must first be write enabled via the WREN instruction.
Then, the instruction and data for the three bits are entered. During the internal write
cycle, all instructions will be ignored except RDSR instructions. The AT25F2048 will
automatically return to write disable state at the completion of the WRSR cycle.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.
Table 8. WPEN Operation
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
ProtectedBlocks
Protected
Protected
Protected
Protected
Protected
Protected
UnprotectedBlocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
READ (READ): Reading the AT25F2048 via the SO (Serial Output) pin requires the fol-
lowing sequence. After the CS line is pulled low to select a device, the Read instruction
is transmitted via the SI line followed by the byte address to be read (Refer to Table 9).
Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the speci-
fied address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The Read instruction can be contin-
ued since the byte address is automatically incremented and data will continue to be
shifted out. When the highest address is reached, the address counter will roll over to
the lowest address allowing the entire memory to be read in one continuous Read
instruction.
PROGRAM (PROGRAM): In order to program the AT25F2048, two separate instruc-
tions must be executed. First, the device must be write enabled via the WREN
instruction. Then the Program instruction can be executed. Also, the address of the
memory location(s) to be programmed must be outside the protected address field loca-
tion selected by the Block Write Protection Level. During an internal self-timed
programming cycle, all commands will be ignored except the RDSR instruction.
The Program instruction requires the following sequence. After the CS line is pulled low
to select the device, the Program instruction is transmitted via the SI line followed by the
byte address and the data (D7-D0) to be programmed (Refer to Table 6). Programming
will start after the CS pin is brought high. The low-to-high transition of the CS pin must
occur during the SCK low time immediately after clocking in the D0 (LSB) data bit for
mode 0.
The Ready/Busy status of the device can be determined by initiating a RDSR instruc-
tion. If Bit 0 = 1, the program cycle is still in progress. If Bit 0 = 0, the program cycle has
ended. Only the RDSR instruction is enabled during the program cycle.
9
2455I–SFLSH–5/07
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AT25F4096W-10SU-2.7 功能描述:IC FLASH 4MBIT 33MHZ 8SOIC RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M(2M x 8,1M x 16) 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP(0.724",18.40mm 宽) 供应商设备封装:48-TSOP 包装:托盘