参数资料
型号: AT25F4096W-10SU-2.7
厂商: Atmel
文件页数: 7/19页
文件大小: 0K
描述: IC FLASH 4MBIT 33MHZ 8SOIC
标准包装: 94
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 4M (512K x 8)
速度: 33MHz
接口: SPI 3 线串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
AT25F4096
Functional
Description
The AT25F4096 is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6800 type series of microcontrollers.
The AT25F4096 utilizes an 8-bit instruction register. The list of instructions and their
operation codes are contained in Table 5. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low transition.
Write is defined as program and/or erase in this specification. The following commands,
Program, Sector Erase, Chip Erase, and WRSR are write instructions for AT25F4096.
Table 5. Instruction Set for the AT25F4096
Instruction
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
PROGRAM
SECTOR ERASE
CHIP ERASE
RDID
Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
0101 X010
0110 X010
0001 X101
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Program Data Into Memory Array
Erase One Sector in Memory Array
Erase All Sectors in Memory Array
Read Manufacturer and Product ID
WRITE ENABLE (WREN): The device will power up in the write disable state when V CC
is applied. All write instructions must therefore be preceded by the WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI
instruction disables all write commands. The WRDI instruction is independent of the sta-
tus of the WP pin.
READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the sta-
tus register. The Ready/Busy and Write Enable status of the device can be determined
by the RDSR instruction. Similarly, the block write protection bits indicate the extent of
protection employed. These bits are set by using the WRSR instruction. During internal
write cycles, all other commands will be ignored except the RDSR instruction.
Table 6. Status Register Format
Bit 7
WPEN
Bit 6
X
Bit 5
X
Bit 4
BP2
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
7
2454G–SFLSH–5/06
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