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参数资料
| 型号： | AT25HP512C1-10CI-2.7 |
| 厂商： | Atmel |
| 文件页数： | 9/21页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 512KBIT 10MHZ 8LAP |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 512K (64K x 8) |
| 速度： | 5MHz，10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TDFN |
| 供应商设备封装： | 8-LAP（5x8） |
| 包装： | 管件 |
| 其它名称： | AT25HP512C10CI2.7 |
AT25HP256/512
Table 7. Read Status Register Bit Definition
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Definition
Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write
cycle is in progress.
Bit 1= “0” indicates the device is not write-enabled. Bit 1 = “1” indicates the
device is write-enabled.
See Table 8.
See Table 8.
Bits 4-6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 9.
Bits 0-7 are “1”s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25HP256/512 is divided into four array seg-
ments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected.
Any of the data within any selected segment will therefore be READ only. The block
write protection levels and corresponding status register control bits are shown in Table
8.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g., WREN, t WC , RDSR).
Table 8. Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
0
1(1/4)
2(1/2)
3(All)
BP1
0
0
1
1
BP0
0
1
0
1
AT25HP256/512
None
6000 - 7FFF/C000 - FFFF
4000 - 7FFF/8000 - FFFF
0000 - 7FFF/0000 - FFFF
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hard-
ware write protected, writes to the status register, including the block protect bits and the
WPEN bit, and the block-protected sections in the memory array are disabled. Writes
are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0” as long as the WP pin is held low.
Table 9. WPEN Operation
WPEN
0
0
1
WP
X
X
Low
WEN
0
1
0
ProtectedBlocks
Protected
Protected
Protected
UnprotectedBlocks
Protected
Writable
Protected
Status Register
Protected
Writable
Protected
9
1113L–SEEPR–3/06
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AT25HP512C1-10CU-1.8 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25HP512C110CU2.7 | 制造商:Atmel Corporation 功能描述:EEPROM Serial-SPI 512K-bit 64K x 8 3.3V/5V 8-Pin LAP |
| AT25HP512C1-10CU-2.7 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25HP512CI-10CI-1.8 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| AT25HP512CI-10CI-2.7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
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