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参数资料
| 型号： | AT28LV010-20TC |
| 厂商： | ATMEL CORP |
| 元件分类： | DRAM |
| 英文描述： | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
| 中文描述： | 128K X 8 EEPROM 3V, 200 ns, PDSO32 |
| 封装： | 8 X 20 MM, PLASTIC, MO-142BD, TSOP1-32 |
| 文件页数： | 3/9页 |
| 文件大小： | 498K |
| 代理商： | AT28LV010-20TC |
Device Operation
READ:
The AT28LV010 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention in their system.
WRITE:
The write operation of the AT28LV010 allows 1 to
128-bytes of data to be written into the device during a
single internal programming period. Each write operation
must be preceded by the software data protection (SDP)
command sequence. This sequence is a series of three
unique write command operations that enable the internal
write circuitry. The command sequence and the data to be
written must conform to the software protected write cycle
timing. Addresses are latched on the falling edge of WE or
CE, whichever occurs last and data is latched on the rising
edge of WE or CE, whichever occurs first. Each succes-
sive byte must be written within 150
μ
s (t
BLC
) of the pre-
vious byte. If the t
BLC
limit is exceeded the AT28LV010 will
cease accepting data and commence the interal program-
ming operation. If more than one data byte is to be written
during a single programming operation, they must reside
on the same page as defined by the state of the A7 - A16
inputs. For each WE high to low transition during the page
write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING:
The AT28LV010 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at anytime during the
write cycle.
TOGGLE BIT:
In addition to DATA Polling the AT28LV010
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling be-
tween one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION:
If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION:
Hardware features protect
against inadvertent writes to the AT28LV010 in the follow-
ing ways: (a) V
CC
power-on delay - once V
CC
has reached
2.0V (typical) the device will automatically time out 5 ms
(typical) before allowing a write: (b) write inhibit - holding
any one of OE low, CE high or WE high inhibits write cy-
cles; (c) noise filter - pulses of less than 15 ns (typical) on
the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION:
The AT28LV010 in-
corporates the industry standard software data protection
(SDP) function. Unlike standard 5-volt only E
2
PROM’s,
the AT28LV010 has SDP enabled at all times. Therefore,
all write operations must be preceded by the SDP com-
mand sequence.
The data in the 3-byte command sequence is not written
to the device; the addresses in the command sequence
can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte se-
quence will start the internal timers. No data will be written
to the device. However, for the duration of t
WC
, read op-
erations will effectively be polling operations.
AT28LV010
2-157
相关PDF资料 |
PDF描述 |
|---|---|
| AT28LV010-20TI | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
| AT28LV010-25 | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
| AT28LV010-25JC | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
| AT28LV010-25JI | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
| AT28LV010-25PC | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT28LV010-20TI | 功能描述:电可擦除可编程只读存储器 1M 3V SDP- 200NS IND TEMP RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| AT28LV010-20TU | 功能描述:电可擦除可编程只读存储器 1M 3V SDP - 200NS IND TEMP RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| AT28LV010-20TU SL319 | 制造商:Atmel Corporation 功能描述:PARALLEL EEPROM, 1M (128K X 8), 3V, SDP - 200NS, TSOP, IND T - Trays |
| AT28LV010-20TU SL383 | 制造商:Atmel Corporation 功能描述:EEPROM PARALLEL 1MBIT 128KX8 3.3V 32TSOP-I - Tape and Reel |
| AT28LV010-20TU-235 | 功能描述:IC EEPROM 1MBIT 200NS 32TSOP 制造商:microchip technology 系列:- 包装:剪切带（CT） 零件状态:在售 存储器类型:非易失 存储器格式:EEPROM 技术:EEPROM 存储容量:1Mb （128K x 8） 写周期时间 - 字，页:10ms 访问时间:200ns 存储器接口:并联 电压 - 电源:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C（TC） 安装类型:表面贴装 封装/外壳:32-TFSOP（0.724"，18.40mm 宽） 供应商器件封装:32-TSOP 标准包装:1 |
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