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参数资料
| 型号： | AT28LV64B-25TI |
| 厂商： | ATMEL CORP |
| 元件分类： | DRAM |
| 英文描述： | High Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State Outputs 20-SOIC -55 to 125 |
| 中文描述： | 8K X 8 EEPROM 3V, 250 ns, PDSO28 |
| 封装： | PLASTIC, TSOP-28 |
| 文件页数： | 7/9页 |
| 文件大小： | 484K |
| 代理商： | AT28LV64B-25TI |
Software Data Protection Write Cycle Waveforms
(1, 2, 3)
Notes: 1. A0 - A12 must conform to the addressing sequence for
the first three bytes as shown above.
2. A6 through A12 must specify the same page address during
each high to low transition of WE (or CE)
after the software code has been entered.
3. OE must be high only when WE and CE are both low.
LOAD LAST BYTE
TO
LAST ADDRESS
LOAD DATA A0
TO
ADDRESS 1555
LOAD DATA 55
TO
ADDRESS 0AAA
LOAD DATA AA
TO
ADDRESS 1555
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A12 - A0 (Hex).
2. Data protect state will be re-activated at
the end of the write cycle.
3. 1 to 64-bytes of data are loaded.
ENTER DATA
PROTECT STATE
WRITES ENABLED
(2)
Write Algorithm
(1)
LOAD DATA XX
TO
ANY ADDRESS
(3)
Symbol
Parameter
Min
Max
Units
t
WC
t
AS
t
AH
t
DS
t
DH
t
WP
t
BLC
t
WPH
Write Cycle Time
10
ms
Address Set-up Time
0
ns
Address Hold Time
100
ns
Data Set-up Time
100
ns
Data Hold Time
0
ns
Write Pulse Width
200
ns
μ
s
ns
Byte Load Cycle Time
100
Write Pulse Width High
100
Page Mode Characteristics
AT28LV64B
2-141
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