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参数资料
| 型号： | AT29C256-12JC |
| 厂商： | ATMEL CORP |
| 元件分类： | DRAM |
| 英文描述： | High Speed CMOS Logic 8-Bit Shift Register with Input Storage 16-PDIP -55 to 125 |
| 中文描述： | 32K X 8 FLASH 5V PROM, 120 ns, PQCC32 |
| 封装： | PLASTIC, MS-016AE, LCC-32 |
| 文件页数： | 3/17页 |
| 文件大小： | 343K |
| 代理商： | AT29C256-12JC |
3
AT29C256
0046P–FLASH–10/04
PROGRAM:
page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded during the programming of its page will be indeterminate. Once the
bytes of a page are loaded into the device, they are simultaneously programmed during
the internal programming period. After the first data byte has been loaded into the
device, successive bytes are entered in the same manner. Each new byte to be pro-
grammed must have its high-to-low transition on WE (or CE) within 150 μs of the low-to-
high transition of WE (or CE) of the preceding byte. If a high-to-low transition is not
detected within 150 μs of the last low-to-high transition, the load period will end and the
internal programming period will start. A6 to A14 specify the page address. The page
address must be valid during each high-to-low transition of WE (or CE). A0 to A5 specify
the byte address within the page. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation has been initiated, and for the
duration of t
WC
, a read operation will effectively be a polling operation.
SOFTWARE DATA PROTECTION:
A software controlled data protection feature is
available on the AT29C256. Once the software protection is enabled a software algo-
rithm must be issued to the device before a program may be performed. The software
protection feature may be enabled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable the software data protection,
a series of three program commands to specific addresses with specific data must be
performed. After the software data protection is enabled the same three program com-
mands must begin each program cycle in order for the programs to occur. All software
program commands must obey the page program timing specifications. Once set, the
software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the soft-
ware feature will guard against inadvertent program cycles during power transitions.
The device is reprogrammed on a page basis. If a byte of data within a
Once set, software data protection will remain active unless the disable command
sequence is issued.
After setting SDP, any attempt to write to the device without the three-byte command
sequence will start the internal write timers. No data will be written to the device; how-
ever, for the duration of t
WC
, a read operation will effectively be a polling operation.
After the software data protection’s three-byte command code is given, a byte load is
performed by applying a low pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling edge of CE or WE, whichever
occurs last. The data is latched by the first rising edge of CE or WE. The 64 bytes of
data must be loaded into each sector by the same procedure as outlined in the program
section under device operation.
HARDWARE DATA PROTECTION:
programs to the AT29C256 in the following ways: (a) V
CC
sense – if V
CC
is below 3.8V
(typical), the program function is inhibited; (b) V
CC
power on delay – once V
CC
has
reached the V
CC
sense level, the device will automatically time out 5 ms (typical) before
programming; (c) Program inhibit – holding any one of OE low, CE high or WE high
inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
Hardware features protect against inadvertent
相关PDF资料 |
PDF描述 |
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| AT29C256-12JI | High Speed CMOS Logic 8-Bit Shift Register with Input Storage 16-SOIC -55 to 125 |
| AT29C256-70TI | High Speed CMOS Logic 4-by-4 Register File 16-SOIC -55 to 125 |
| AT29C256-90JC | High Speed CMOS Logic 4-by-4 Register File 16-SOIC -55 to 125 |
| AT29C256-90JI | High Speed CMOS Logic 4-by-4 Register File 16-SOIC -55 to 125 |
| AT29C256-90PC | High Speed CMOS Logic 4-by-4 Register File 16-SOIC -55 to 125 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT29C256-12JC-T | 功能描述:IC FLASH 256KBIT 120NS 32PLCC 制造商:microchip technology 系列:- 包装:带卷（TR） 零件状态:停產 存储器类型:非易失 存储器格式:闪存 技术:FLASH 存储容量:256Kb （32K x 8） 写周期时间 - 字，页:10ms 访问时间:120ns 存储器接口:并联 电压 - 电源:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C（TC） 安装类型:表面贴装 封装/外壳:32-LCC（J 形引线） 供应商器件封装:32-PLCC（11.43x13.97） 基本零件编号:AT29C256 标准包装:750 |
| AT29C256-12JI | 功能描述:闪存 256k (32kx8) RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AT29C256-12JI-T | 功能描述:IC FLASH 256KBIT 120NS 32PLCC 制造商:microchip technology 系列:- 包装:带卷（TR） 零件状态:停產 存储器类型:非易失 存储器格式:闪存 技术:FLASH 存储容量:256Kb （32K x 8） 写周期时间 - 字，页:10ms 访问时间:120ns 存储器接口:并联 电压 - 电源:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C（TC） 安装类型:表面贴装 封装/外壳:32-LCC（J 形引线） 供应商器件封装:32-PLCC（11.43x13.97） 基本零件编号:AT29C256 标准包装:750 |
| AT29C256-12LC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Flash EEPROM |
| AT29C256-12LI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Flash EEPROM |
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